1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
17 #include <generic-phy.h>
18 #include <phy-sun4i-usb.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/display.h>
22 #include <asm/arch/dram.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc.h>
25 #include <asm/arch/spl.h>
27 #include <asm/armv7.h>
32 #include <environment.h>
33 #include <linux/libfdt.h>
38 #include <asm/setup.h>
40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
42 int soft_i2c_gpio_sda;
43 int soft_i2c_gpio_scl;
45 static int soft_i2c_board_init(void)
49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
50 if (soft_i2c_gpio_sda < 0) {
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
53 return soft_i2c_gpio_sda;
55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
63 if (soft_i2c_gpio_scl < 0) {
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
66 return soft_i2c_gpio_scl;
68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
78 static int soft_i2c_board_init(void) { return 0; }
81 DECLARE_GLOBAL_DATA_PTR;
83 void i2c_init_board(void)
85 #ifdef CONFIG_I2C0_ENABLE
86 #if defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN5I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
92 clock_twi_onoff(0, 1);
93 #elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
96 clock_twi_onoff(0, 1);
97 #elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
104 #ifdef CONFIG_I2C1_ENABLE
105 #if defined(CONFIG_MACH_SUN4I) || \
106 defined(CONFIG_MACH_SUN7I) || \
107 defined(CONFIG_MACH_SUN8I_R40)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
110 clock_twi_onoff(1, 1);
111 #elif defined(CONFIG_MACH_SUN5I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
114 clock_twi_onoff(1, 1);
115 #elif defined(CONFIG_MACH_SUN6I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
118 clock_twi_onoff(1, 1);
119 #elif defined(CONFIG_MACH_SUN8I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
122 clock_twi_onoff(1, 1);
126 #ifdef CONFIG_I2C2_ENABLE
127 #if defined(CONFIG_MACH_SUN4I) || \
128 defined(CONFIG_MACH_SUN7I) || \
129 defined(CONFIG_MACH_SUN8I_R40)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
132 clock_twi_onoff(2, 1);
133 #elif defined(CONFIG_MACH_SUN5I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
135 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
136 clock_twi_onoff(2, 1);
137 #elif defined(CONFIG_MACH_SUN6I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
140 clock_twi_onoff(2, 1);
141 #elif defined(CONFIG_MACH_SUN8I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
144 clock_twi_onoff(2, 1);
148 #ifdef CONFIG_I2C3_ENABLE
149 #if defined(CONFIG_MACH_SUN6I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
151 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
152 clock_twi_onoff(3, 1);
153 #elif defined(CONFIG_MACH_SUN7I) || \
154 defined(CONFIG_MACH_SUN8I_R40)
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
156 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
157 clock_twi_onoff(3, 1);
161 #ifdef CONFIG_I2C4_ENABLE
162 #if defined(CONFIG_MACH_SUN7I) || \
163 defined(CONFIG_MACH_SUN8I_R40)
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
165 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
166 clock_twi_onoff(4, 1);
170 #ifdef CONFIG_R_I2C_ENABLE
171 clock_twi_onoff(5, 1);
172 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
177 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
178 enum env_location env_get_location(enum env_operation op, int prio)
193 /* add board specific code here */
196 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
198 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
201 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
202 debug("id_pfr1: 0x%08x\n", id_pfr1);
203 /* Generic Timer Extension available? */
204 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
207 debug("Setting CNTFRQ\n");
210 * CNTFRQ is a secure register, so we will crash if we try to
211 * write this from the non-secure world (read is OK, though).
212 * In case some bootcode has already set the correct value,
213 * we avoid the risk of writing to it.
215 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
216 if (freq != COUNTER_FREQUENCY) {
217 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
218 freq, COUNTER_FREQUENCY);
219 #ifdef CONFIG_NON_SECURE
220 printf("arch timer frequency is wrong, but cannot adjust it\n");
222 asm volatile("mcr p15, 0, %0, c14, c0, 0"
223 : : "r"(COUNTER_FREQUENCY));
227 #endif /* !CONFIG_ARM64 */
229 ret = axp_gpio_init();
233 #ifdef CONFIG_SATAPWR
234 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
235 gpio_request(satapwr_pin, "satapwr");
236 gpio_direction_output(satapwr_pin, 1);
237 /* Give attached sata device time to power-up to avoid link timeouts */
241 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
242 gpio_request(macpwr_pin, "macpwr");
243 gpio_direction_output(macpwr_pin, 1);
248 * Temporary workaround for enabling I2C clocks until proper sunxi DM
249 * clk, reset and pinctrl drivers land.
254 /* Uses dm gpio code so do this here and not in i2c_init_board() */
255 return soft_i2c_board_init();
259 * On older SoCs the SPL is actually at address zero, so using NULL as
260 * an error value does not work.
262 #define INVALID_SPL_HEADER ((void *)~0UL)
264 static struct boot_file_head * get_spl_header(uint8_t req_version)
266 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
267 uint8_t spl_header_version = spl->spl_signature[3];
269 /* Is there really the SPL header (still) there? */
270 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
271 return INVALID_SPL_HEADER;
273 if (spl_header_version < req_version) {
274 printf("sunxi SPL version mismatch: expected %u, got %u\n",
275 req_version, spl_header_version);
276 return INVALID_SPL_HEADER;
284 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
286 if (spl == INVALID_SPL_HEADER)
287 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
290 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
292 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
293 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
298 #if defined(CONFIG_NAND_SUNXI)
299 static void nand_pinmux_setup(void)
303 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
304 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
306 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
307 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
308 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
310 /* sun4i / sun7i do have a PC23, but it is not used for nand,
311 * only sun7i has a PC24 */
312 #ifdef CONFIG_MACH_SUN7I
313 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
317 static void nand_clock_setup(void)
319 struct sunxi_ccm_reg *const ccm =
320 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
322 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
323 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
324 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
325 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
327 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
330 void board_nand_init(void)
334 #ifndef CONFIG_SPL_BUILD
341 static void mmc_pinmux_setup(int sdc)
344 __maybe_unused int pins;
349 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
350 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
351 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
352 sunxi_gpio_set_drv(pin, 2);
357 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
359 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
360 defined(CONFIG_MACH_SUN8I_R40)
361 if (pins == SUNXI_GPIO_H) {
362 /* SDC1: PH22-PH-27 */
363 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
364 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
365 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
366 sunxi_gpio_set_drv(pin, 2);
370 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
371 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
372 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
373 sunxi_gpio_set_drv(pin, 2);
376 #elif defined(CONFIG_MACH_SUN5I)
378 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
379 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
380 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
381 sunxi_gpio_set_drv(pin, 2);
383 #elif defined(CONFIG_MACH_SUN6I)
385 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
386 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
387 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
388 sunxi_gpio_set_drv(pin, 2);
390 #elif defined(CONFIG_MACH_SUN8I)
391 if (pins == SUNXI_GPIO_D) {
393 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
394 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
395 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
396 sunxi_gpio_set_drv(pin, 2);
400 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
401 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
402 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
403 sunxi_gpio_set_drv(pin, 2);
410 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
412 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
414 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
415 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
416 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
417 sunxi_gpio_set_drv(pin, 2);
419 #elif defined(CONFIG_MACH_SUN5I)
420 if (pins == SUNXI_GPIO_E) {
422 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
423 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
424 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
425 sunxi_gpio_set_drv(pin, 2);
429 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
430 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
431 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
432 sunxi_gpio_set_drv(pin, 2);
435 #elif defined(CONFIG_MACH_SUN6I)
436 if (pins == SUNXI_GPIO_A) {
438 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
439 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
440 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
441 sunxi_gpio_set_drv(pin, 2);
444 /* SDC2: PC6-PC15, PC24 */
445 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
446 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
447 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
448 sunxi_gpio_set_drv(pin, 2);
451 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
452 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
455 #elif defined(CONFIG_MACH_SUN8I_R40)
456 /* SDC2: PC6-PC15, PC24 */
457 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
463 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
464 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
466 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
467 /* SDC2: PC5-PC6, PC8-PC16 */
468 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
469 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
470 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
471 sunxi_gpio_set_drv(pin, 2);
474 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
479 #elif defined(CONFIG_MACH_SUN50I_H6)
481 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
482 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
483 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
484 sunxi_gpio_set_drv(pin, 2);
486 #elif defined(CONFIG_MACH_SUN9I)
488 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
489 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
490 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
491 sunxi_gpio_set_drv(pin, 2);
497 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
499 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
500 defined(CONFIG_MACH_SUN8I_R40)
502 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
503 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
504 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
505 sunxi_gpio_set_drv(pin, 2);
507 #elif defined(CONFIG_MACH_SUN6I)
508 if (pins == SUNXI_GPIO_A) {
510 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
516 /* SDC3: PC6-PC15, PC24 */
517 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
518 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
519 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
520 sunxi_gpio_set_drv(pin, 2);
523 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
524 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
531 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
536 int board_mmc_init(bd_t *bis)
538 __maybe_unused struct mmc *mmc0, *mmc1;
540 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
541 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
545 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
546 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
547 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
556 #ifdef CONFIG_SPL_BUILD
558 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
560 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
562 if (spl == INVALID_SPL_HEADER)
565 /* Promote the header version for U-Boot proper, if needed. */
566 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
567 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
569 spl->dram_size = dram_size >> 20;
572 void sunxi_board_init(void)
574 int power_failed = 0;
576 #ifdef CONFIG_SY8106A_POWER
577 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
580 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
581 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
582 defined CONFIG_AXP818_POWER
583 power_failed = axp_init();
585 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
586 defined CONFIG_AXP818_POWER
587 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
589 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
590 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
591 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
592 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
594 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
595 defined CONFIG_AXP818_POWER
596 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
599 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
600 defined CONFIG_AXP818_POWER
601 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
603 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
604 #if !defined(CONFIG_AXP152_POWER)
605 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
607 #ifdef CONFIG_AXP209_POWER
608 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
611 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
612 defined(CONFIG_AXP818_POWER)
613 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
614 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
615 #if !defined CONFIG_AXP809_POWER
616 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
617 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
619 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
620 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
621 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
624 #ifdef CONFIG_AXP818_POWER
625 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
626 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
627 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
630 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
631 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
635 gd->ram_size = sunxi_dram_init();
636 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
640 sunxi_spl_store_dram_size(gd->ram_size);
643 * Only clock up the CPU to full speed if we are reasonably
644 * assured it's being powered with suitable core voltage
647 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
649 printf("Failed to set core voltage! Can't set CPU frequency\n");
653 #ifdef CONFIG_USB_GADGET
654 int g_dnl_board_usb_cable_connected(void)
660 ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
662 pr_err("%s: Cannot find USB device\n", __func__);
666 ret = generic_phy_get_by_name(dev, "usb", &phy);
668 pr_err("failed to get %s USB PHY\n", dev->name);
672 ret = generic_phy_init(&phy);
674 pr_err("failed to init %s USB PHY\n", dev->name);
678 ret = sun4i_usb_phy_vbus_detect(&phy);
680 pr_err("A charger is plugged into the OTG\n");
688 #ifdef CONFIG_SERIAL_TAG
689 void get_board_serial(struct tag_serialnr *serialnr)
692 unsigned long long serial;
694 serial_string = env_get("serial#");
697 serial = simple_strtoull(serial_string, NULL, 16);
699 serialnr->high = (unsigned int) (serial >> 32);
700 serialnr->low = (unsigned int) (serial & 0xffffffff);
709 * Check the SPL header for the "sunxi" variant. If found: parse values
710 * that might have been passed by the loader ("fel" utility), and update
711 * the environment accordingly.
713 static void parse_spl_header(const uint32_t spl_addr)
715 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
717 if (spl == INVALID_SPL_HEADER)
720 if (!spl->fel_script_address)
723 if (spl->fel_uEnv_length != 0) {
725 * data is expected in uEnv.txt compatible format, so "env
726 * import -t" the string(s) at fel_script_address right away.
728 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
729 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
732 /* otherwise assume .scr format (mkimage-type script) */
733 env_set_hex("fel_scriptaddr", spl->fel_script_address);
737 * Note this function gets called multiple times.
738 * It must not make any changes to env variables which already exist.
740 static void setup_environment(const void *fdt)
742 char serial_string[17] = { 0 };
748 ret = sunxi_get_sid(sid);
749 if (ret == 0 && sid[0] != 0) {
751 * The single words 1 - 3 of the SID have quite a few bits
752 * which are the same on many models, so we take a crc32
753 * of all 3 words, to get a more unique value.
755 * Note we only do this on newer SoCs as we cannot change
756 * the algorithm on older SoCs since those have been using
757 * fixed mac-addresses based on only using word 3 for a
758 * long time and changing a fixed mac-address with an
759 * u-boot update is not good.
761 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
762 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
763 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
764 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
767 /* Ensure the NIC specific bytes of the mac are not all 0 */
768 if ((sid[3] & 0xffffff) == 0)
771 for (i = 0; i < 4; i++) {
772 sprintf(ethaddr, "ethernet%d", i);
773 if (!fdt_get_alias(fdt, ethaddr))
777 strcpy(ethaddr, "ethaddr");
779 sprintf(ethaddr, "eth%daddr", i);
781 if (env_get(ethaddr))
784 /* Non OUI / registered MAC address */
785 mac_addr[0] = (i << 4) | 0x02;
786 mac_addr[1] = (sid[0] >> 0) & 0xff;
787 mac_addr[2] = (sid[3] >> 24) & 0xff;
788 mac_addr[3] = (sid[3] >> 16) & 0xff;
789 mac_addr[4] = (sid[3] >> 8) & 0xff;
790 mac_addr[5] = (sid[3] >> 0) & 0xff;
792 eth_env_set_enetaddr(ethaddr, mac_addr);
795 if (!env_get("serial#")) {
796 snprintf(serial_string, sizeof(serial_string),
797 "%08x%08x", sid[0], sid[3]);
799 env_set("serial#", serial_string);
804 int misc_init_r(void)
808 env_set("fel_booted", NULL);
809 env_set("fel_scriptaddr", NULL);
810 env_set("mmc_bootdev", NULL);
812 boot = sunxi_get_boot_device();
813 /* determine if we are running in FEL mode */
814 if (boot == BOOT_DEVICE_BOARD) {
815 env_set("fel_booted", "1");
816 parse_spl_header(SPL_ADDR);
817 /* or if we booted from MMC, and which one */
818 } else if (boot == BOOT_DEVICE_MMC1) {
819 env_set("mmc_bootdev", "0");
820 } else if (boot == BOOT_DEVICE_MMC2) {
821 env_set("mmc_bootdev", "1");
824 setup_environment(gd->fdt_blob);
826 #ifdef CONFIG_USB_ETHER
833 int ft_board_setup(void *blob, bd_t *bd)
835 int __maybe_unused r;
838 * Call setup_environment again in case the boot fdt has
839 * ethernet aliases the u-boot copy does not have.
841 setup_environment(blob);
843 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
844 r = sunxi_simplefb_setup(blob);
851 #ifdef CONFIG_SPL_LOAD_FIT
852 int board_fit_config_name_match(const char *name)
854 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
855 const char *cmp_str = (const char *)spl;
857 /* Check if there is a DT name stored in the SPL header and use that. */
858 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
859 cmp_str += spl->dt_name_offset;
861 #ifdef CONFIG_DEFAULT_DEVICE_TREE
862 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
868 #ifdef CONFIG_PINE64_DT_SELECTION
869 /* Differentiate the two Pine64 board DTs by their DRAM size. */
870 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
871 if ((gd->ram_size > 512 * 1024 * 1024))
872 return !strstr(name, "plus");
874 return !!strstr(name, "plus");
876 return strcmp(name, cmp_str);
879 return strcmp(name, cmp_str);