4 default " Allwinner Technology"
6 config PRE_CONSOLE_BUFFER
9 config SPL_GPIO_SUPPORT
12 config SPL_LIBCOMMON_SUPPORT
15 config SPL_LIBDISK_SUPPORT
18 config SPL_LIBGENERIC_SUPPORT
21 config SPL_MMC_SUPPORT
24 config SPL_POWER_SUPPORT
27 config SPL_SERIAL_SUPPORT
30 config SUNXI_HIGH_SRAM
34 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
35 with the first SRAM region being located at address 0.
36 Some newer SoCs map the boot ROM at address 0 instead and move the
37 SRAM to 64KB, just behind the mask ROM.
38 Chips using the latter setup are supposed to select this option to
39 adjust the addresses accordingly.
41 # Note only one of these may be selected at a time! But hidden choices are
42 # not supported by Kconfig
43 config SUNXI_GEN_SUN4I
46 Select this for sunxi SoCs which have resets and clocks set up
47 as the original A10 (mach-sun4i).
49 config SUNXI_GEN_SUN6I
52 Select this for sunxi SoCs which have sun6i like periphery, like
53 separate ahb reset control registers, custom pmic bus, new style
57 config MACH_SUNXI_H3_H5
59 select SUNXI_GEN_SUN6I
63 prompt "Sunxi SoC Variant"
67 bool "sun4i (Allwinner A10)"
69 select ARM_CORTEX_CPU_IS_UP
70 select SUNXI_GEN_SUN4I
74 bool "sun5i (Allwinner A13)"
76 select ARM_CORTEX_CPU_IS_UP
77 select SUNXI_GEN_SUN4I
81 bool "sun6i (Allwinner A31)"
83 select CPU_V7_HAS_NONSEC
84 select CPU_V7_HAS_VIRT
85 select ARCH_SUPPORT_PSCI
86 select SUNXI_GEN_SUN6I
88 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
91 bool "sun7i (Allwinner A20)"
93 select CPU_V7_HAS_NONSEC
94 select CPU_V7_HAS_VIRT
95 select ARCH_SUPPORT_PSCI
96 select SUNXI_GEN_SUN4I
98 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
100 config MACH_SUN8I_A23
101 bool "sun8i (Allwinner A23)"
103 select CPU_V7_HAS_NONSEC
104 select CPU_V7_HAS_VIRT
105 select ARCH_SUPPORT_PSCI
106 select SUNXI_GEN_SUN6I
108 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
110 config MACH_SUN8I_A33
111 bool "sun8i (Allwinner A33)"
113 select CPU_V7_HAS_NONSEC
114 select CPU_V7_HAS_VIRT
115 select ARCH_SUPPORT_PSCI
116 select SUNXI_GEN_SUN6I
118 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
120 config MACH_SUN8I_A83T
121 bool "sun8i (Allwinner A83T)"
123 select SUNXI_GEN_SUN6I
127 bool "sun8i (Allwinner H3)"
129 select CPU_V7_HAS_NONSEC
130 select CPU_V7_HAS_VIRT
131 select ARCH_SUPPORT_PSCI
132 select MACH_SUNXI_H3_H5
133 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 bool "sun9i (Allwinner A80)"
138 select SUNXI_HIGH_SRAM
139 select SUNXI_GEN_SUN6I
143 bool "sun50i (Allwinner A64)"
145 select SUNXI_GEN_SUN6I
146 select SUNXI_HIGH_SRAM
151 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
154 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
156 config RESERVE_ALLWINNER_BOOT0_HEADER
157 bool "reserve space for Allwinner boot0 header"
158 select ENABLE_ARM_SOC_BOOT0_HOOK
160 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
161 filled with magic values post build. The Allwinner provided boot0
162 blob relies on this information to load and execute U-Boot.
163 Only needed on 64-bit Allwinner boards so far when using boot0.
165 config ARM_BOOT_HOOK_RMR
169 select ENABLE_ARM_SOC_BOOT0_HOOK
171 Insert some ARM32 code at the very beginning of the U-Boot binary
172 which uses an RMR register write to bring the core into AArch64 mode.
173 The very first instruction acts as a switch, since it's carefully
174 chosen to be a NOP in one mode and a branch in the other, so the
175 code would only be executed if not already in AArch64.
176 This allows both the SPL and the U-Boot proper to be entered in
177 either mode and switch to AArch64 if needed.
180 int "sunxi dram type"
181 depends on MACH_SUN8I_A83T
184 Set the dram type, 3: DDR3, 7: LPDDR3
187 int "sunxi dram clock speed"
188 default 792 if MACH_SUN9I
189 default 312 if MACH_SUN6I || MACH_SUN8I
190 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
191 default 672 if MACH_SUN50I
193 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
194 must be a multiple of 24. For the sun9i (A80), the tested values
195 (for DDR3-1600) are 312 to 792.
197 if MACH_SUN5I || MACH_SUN7I
199 int "sunxi mbus clock speed"
202 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
207 int "sunxi dram zq value"
208 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
209 default 127 if MACH_SUN7I
210 default 4145117 if MACH_SUN9I
211 default 3881915 if MACH_SUN50I
213 Set the dram zq value.
216 bool "sunxi dram odt enable"
217 default n if !MACH_SUN8I_A23
218 default y if MACH_SUN8I_A23
219 default y if MACH_SUN50I
221 Select this to enable dram odt (on die termination).
223 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
225 int "sunxi dram emr1 value"
226 default 0 if MACH_SUN4I
227 default 4 if MACH_SUN5I || MACH_SUN7I
229 Set the dram controller emr1 value.
232 hex "sunxi dram tpr3 value"
235 Set the dram controller tpr3 parameter. This parameter configures
236 the delay on the command lane and also phase shifts, which are
237 applied for sampling incoming read data. The default value 0
238 means that no phase/delay adjustments are necessary. Properly
239 configuring this parameter increases reliability at high DRAM
242 config DRAM_DQS_GATING_DELAY
243 hex "sunxi dram dqs_gating_delay value"
246 Set the dram controller dqs_gating_delay parmeter. Each byte
247 encodes the DQS gating delay for each byte lane. The delay
248 granularity is 1/4 cycle. For example, the value 0x05060606
249 means that the delay is 5 quarter-cycles for one lane (1.25
250 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
251 The default value 0 means autodetection. The results of hardware
252 autodetection are not very reliable and depend on the chip
253 temperature (sometimes producing different results on cold start
254 and warm reboot). But the accuracy of hardware autodetection
255 is usually good enough, unless running at really high DRAM
256 clocks speeds (up to 600MHz). If unsure, keep as 0.
259 prompt "sunxi dram timings"
260 default DRAM_TIMINGS_VENDOR_MAGIC
262 Select the timings of the DDR3 chips.
264 config DRAM_TIMINGS_VENDOR_MAGIC
265 bool "Magic vendor timings from Android"
267 The same DRAM timings as in the Allwinner boot0 bootloader.
269 config DRAM_TIMINGS_DDR3_1066F_1333H
270 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
272 Use the timings of the standard JEDEC DDR3-1066F speed bin for
273 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
274 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
275 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
276 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
277 that down binning to DDR3-1066F is supported (because DDR3-1066F
278 uses a bit faster timings than DDR3-1333H).
280 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
281 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
283 Use the timings of the slowest possible JEDEC speed bin for the
284 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
285 DDR3-800E, DDR3-1066G or DDR3-1333J.
292 config DRAM_ODT_CORRECTION
293 int "sunxi dram odt correction value"
296 Set the dram odt correction value (range -255 - 255). In allwinner
297 fex files, this option is found in bits 8-15 of the u32 odt_en variable
298 in the [dram] section. When bit 31 of the odt_en variable is set
299 then the correction is negative. Usually the value for this is 0.
303 default 816000000 if MACH_SUN50I
304 default 912000000 if MACH_SUN7I
305 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
307 config SYS_CONFIG_NAME
308 default "sun4i" if MACH_SUN4I
309 default "sun5i" if MACH_SUN5I
310 default "sun6i" if MACH_SUN6I
311 default "sun7i" if MACH_SUN7I
312 default "sun8i" if MACH_SUN8I
313 default "sun9i" if MACH_SUN9I
314 default "sun50i" if MACH_SUN50I
323 bool "UART0 on MicroSD breakout board"
326 Repurpose the SD card slot for getting access to the UART0 serial
327 console. Primarily useful only for low level u-boot debugging on
328 tablets, where normal UART0 is difficult to access and requires
329 device disassembly and/or soldering. As the SD card can't be used
330 at the same time, the system can be only booted in the FEL mode.
331 Only enable this if you really know what you are doing.
333 config OLD_SUNXI_KERNEL_COMPAT
334 bool "Enable workarounds for booting old kernels"
337 Set this to enable various workarounds for old kernels, this results in
338 sub-optimal settings for newer kernels, only enable if needed.
341 string "Card detect pin for mmc0"
342 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
345 Set the card detect pin for mmc0, leave empty to not use cd. This
346 takes a string in the format understood by sunxi_name_to_gpio, e.g.
347 PH1 for pin 1 of port H.
350 string "Card detect pin for mmc1"
353 See MMC0_CD_PIN help text.
356 string "Card detect pin for mmc2"
359 See MMC0_CD_PIN help text.
362 string "Card detect pin for mmc3"
365 See MMC0_CD_PIN help text.
368 string "Pins for mmc1"
371 Set the pins used for mmc1, when applicable. This takes a string in the
372 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
375 string "Pins for mmc2"
378 See MMC1_PINS help text.
381 string "Pins for mmc3"
384 See MMC1_PINS help text.
386 config MMC_SUNXI_SLOT_EXTRA
387 int "mmc extra slot number"
390 sunxi builds always enable mmc0, some boards also have a second sdcard
391 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
394 config INITIAL_USB_SCAN_DELAY
395 int "delay initial usb scan by x ms to allow builtin devices to init"
398 Some boards have on board usb devices which need longer than the
399 USB spec's 1 second to connect from board powerup. Set this config
400 option to a non 0 value to add an extra delay before the first usb
404 string "Vbus enable pin for usb0 (otg)"
407 Set the Vbus enable pin for usb0 (otg). This takes a string in the
408 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
411 string "Vbus detect pin for usb0 (otg)"
414 Set the Vbus detect pin for usb0 (otg). This takes a string in the
415 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
418 string "ID detect pin for usb0 (otg)"
421 Set the ID detect pin for usb0 (otg). This takes a string in the
422 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
425 string "Vbus enable pin for usb1 (ehci0)"
426 default "PH6" if MACH_SUN4I || MACH_SUN7I
427 default "PH27" if MACH_SUN6I
429 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
430 a string in the format understood by sunxi_name_to_gpio, e.g.
431 PH1 for pin 1 of port H.
434 string "Vbus enable pin for usb2 (ehci1)"
435 default "PH3" if MACH_SUN4I || MACH_SUN7I
436 default "PH24" if MACH_SUN6I
438 See USB1_VBUS_PIN help text.
441 string "Vbus enable pin for usb3 (ehci2)"
444 See USB1_VBUS_PIN help text.
447 bool "Enable I2C/TWI controller 0"
448 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
449 default n if MACH_SUN6I || MACH_SUN8I
452 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
453 its clock and setting up the bus. This is especially useful on devices
454 with slaves connected to the bus or with pins exposed through e.g. an
455 expansion port/header.
458 bool "Enable I2C/TWI controller 1"
462 See I2C0_ENABLE help text.
465 bool "Enable I2C/TWI controller 2"
469 See I2C0_ENABLE help text.
471 if MACH_SUN6I || MACH_SUN7I
473 bool "Enable I2C/TWI controller 3"
477 See I2C0_ENABLE help text.
482 bool "Enable the PRCM I2C/TWI controller"
483 # This is used for the pmic on H3
484 default y if SY8106A_POWER
487 Set this to y to enable the I2C controller which is part of the PRCM.
492 bool "Enable I2C/TWI controller 4"
496 See I2C0_ENABLE help text.
500 bool "Enable support for gpio-s on axp PMICs"
503 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
506 bool "Enable graphical uboot console on HDMI, LCD or VGA"
507 depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
510 Say Y here to add support for using a cfb console on the HDMI, LCD
511 or VGA output found on most sunxi devices. See doc/README.video for
512 info on how to select the video output and mode.
515 bool "HDMI output support"
516 depends on VIDEO && !MACH_SUN8I
519 Say Y here to add support for outputting video over HDMI.
522 bool "VGA output support"
523 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
526 Say Y here to add support for outputting video over VGA.
528 config VIDEO_VGA_VIA_LCD
529 bool "VGA via LCD controller support"
530 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
533 Say Y here to add support for external DACs connected to the parallel
534 LCD interface driving a VGA connector, such as found on the
537 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
538 bool "Force sync active high for VGA via LCD controller support"
539 depends on VIDEO_VGA_VIA_LCD
542 Say Y here if you've a board which uses opendrain drivers for the vga
543 hsync and vsync signals. Opendrain drivers cannot generate steep enough
544 positive edges for a stable video output, so on boards with opendrain
545 drivers the sync signals must always be active high.
547 config VIDEO_VGA_EXTERNAL_DAC_EN
548 string "LCD panel power enable pin"
549 depends on VIDEO_VGA_VIA_LCD
552 Set the enable pin for the external VGA DAC. This takes a string in the
553 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
555 config VIDEO_COMPOSITE
556 bool "Composite video output support"
557 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
560 Say Y here to add support for outputting composite video.
562 config VIDEO_LCD_MODE
563 string "LCD panel timing details"
567 LCD panel timing details string, leave empty if there is no LCD panel.
568 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
569 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
570 Also see: http://linux-sunxi.org/LCD
572 config VIDEO_LCD_DCLK_PHASE
573 int "LCD panel display clock phase"
577 Select LCD panel display clock phase shift, range 0-3.
579 config VIDEO_LCD_POWER
580 string "LCD panel power enable pin"
584 Set the power enable pin for the LCD panel. This takes a string in the
585 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
587 config VIDEO_LCD_RESET
588 string "LCD panel reset pin"
592 Set the reset pin for the LCD panel. This takes a string in the format
593 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
595 config VIDEO_LCD_BL_EN
596 string "LCD panel backlight enable pin"
600 Set the backlight enable pin for the LCD panel. This takes a string in the
601 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
604 config VIDEO_LCD_BL_PWM
605 string "LCD panel backlight pwm pin"
609 Set the backlight pwm pin for the LCD panel. This takes a string in the
610 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
612 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
613 bool "LCD panel backlight pwm is inverted"
617 Set this if the backlight pwm output is active low.
619 config VIDEO_LCD_PANEL_I2C
620 bool "LCD panel needs to be configured via i2c"
625 Say y here if the LCD panel needs to be configured via i2c. This
626 will add a bitbang i2c controller using gpios to talk to the LCD.
628 config VIDEO_LCD_PANEL_I2C_SDA
629 string "LCD panel i2c interface SDA pin"
630 depends on VIDEO_LCD_PANEL_I2C
633 Set the SDA pin for the LCD i2c interface. This takes a string in the
634 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
636 config VIDEO_LCD_PANEL_I2C_SCL
637 string "LCD panel i2c interface SCL pin"
638 depends on VIDEO_LCD_PANEL_I2C
641 Set the SCL pin for the LCD i2c interface. This takes a string in the
642 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
645 # Note only one of these may be selected at a time! But hidden choices are
646 # not supported by Kconfig
647 config VIDEO_LCD_IF_PARALLEL
650 config VIDEO_LCD_IF_LVDS
655 prompt "LCD panel support"
658 Select which type of LCD panel to support.
660 config VIDEO_LCD_PANEL_PARALLEL
661 bool "Generic parallel interface LCD panel"
662 select VIDEO_LCD_IF_PARALLEL
664 config VIDEO_LCD_PANEL_LVDS
665 bool "Generic lvds interface LCD panel"
666 select VIDEO_LCD_IF_LVDS
668 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
669 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
670 select VIDEO_LCD_SSD2828
671 select VIDEO_LCD_IF_PARALLEL
673 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
675 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
676 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
677 select VIDEO_LCD_ANX9804
678 select VIDEO_LCD_IF_PARALLEL
679 select VIDEO_LCD_PANEL_I2C
681 Select this for eDP LCD panels with 4 lanes running at 1.62G,
682 connected via an ANX9804 bridge chip.
684 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
685 bool "Hitachi tx18d42vm LCD panel"
686 select VIDEO_LCD_HITACHI_TX18D42VM
687 select VIDEO_LCD_IF_LVDS
689 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
691 config VIDEO_LCD_TL059WV5C0
692 bool "tl059wv5c0 LCD panel"
693 select VIDEO_LCD_PANEL_I2C
694 select VIDEO_LCD_IF_PARALLEL
696 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
697 Aigo M60/M608/M606 tablets.
703 int "GMAC Transmit Clock Delay Chain"
706 Set the GMAC Transmit Clock Delay Chain value.
708 config SPL_STACK_R_ADDR
709 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
710 default 0x2fe00000 if MACH_SUN9I