1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
9 #include <asm/arch/ddr.h>
10 #include <power/pmic.h>
11 #include <power/stpmic1.h>
13 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
14 void board_debug_uart_init(void)
16 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
19 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
21 /* UART4 clock enable */
22 setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
24 #define GPIOG_BASE 0x50008000
25 /* GPIOG clock enable */
26 writel(BIT(6), RCC_MP_AHB4ENSETR);
27 /* GPIO configuration for EVAL board
30 writel(0xffbfffff, GPIOG_BASE + 0x00);
31 writel(0x00006000, GPIOG_BASE + 0x24);
34 #error("CONFIG_DEBUG_UART_BASE: not supported value")
40 #ifdef CONFIG_PMIC_STPMIC1
41 int board_ddr_power_init(enum ddr_type ddr_type)
44 bool buck3_at_1800000v = false;
47 ret = uclass_get_device_by_driver(UCLASS_PMIC,
48 DM_GET_DRIVER(pmic_stpmic1), &dev);
50 /* No PMIC on board */
55 /* VTT = Set LDO3 to sync mode */
56 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
60 ret &= ~STPMIC1_LDO3_MODE;
61 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
62 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
64 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
69 /* VDD_DDR = Set BUCK2 to 1.35V */
70 ret = pmic_clrsetbits(dev,
71 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
72 STPMIC1_BUCK_VOUT_MASK,
73 STPMIC1_BUCK2_1350000V);
77 /* Enable VDD_DDR = BUCK2 */
78 ret = pmic_clrsetbits(dev,
79 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
80 STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
84 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
87 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
88 STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
92 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
94 /* Enable VTT = LDO3 */
95 ret = pmic_clrsetbits(dev,
96 STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
97 STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
101 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
108 * configure VDD_DDR1 = LDO3
110 * + bypass mode if BUCK3 = 1.8V
111 * + normal mode if BUCK3 != 1.8V
113 ret = pmic_reg_read(dev,
114 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
118 if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
119 buck3_at_1800000v = true;
121 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
125 ret &= ~STPMIC1_LDO3_MODE;
126 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
127 ret |= STPMIC1_LDO3_1800000;
128 if (buck3_at_1800000v)
129 ret |= STPMIC1_LDO3_MODE;
131 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
136 /* VDD_DDR2 : Set BUCK2 to 1.2V */
137 ret = pmic_clrsetbits(dev,
138 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
139 STPMIC1_BUCK_VOUT_MASK,
140 STPMIC1_BUCK2_1200000V);
144 /* Enable VDD_DDR1 = LDO3 */
145 ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
146 STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
150 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
152 /* Enable VDD_DDR2 =BUCK2 */
153 ret = pmic_clrsetbits(dev,
154 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
155 STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
159 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
162 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
163 STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
167 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);