board/st/stm32mp1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/ddr.h>
  10 #include <linux/bitops.h>
  11 #include <linux/delay.h>
  12 #include <power/pmic.h>
  13 #include <power/stpmic1.h>
  14
  15 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  16 void board_debug_uart_init(void)
  17 {
  18 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
  19
  20 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
  21 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
  22
  23         /* UART4 clock enable */
  24         setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
  25
  26 #define GPIOG_BASE 0x50008000
  27         /* GPIOG clock enable */
  28         writel(BIT(6), RCC_MP_AHB4ENSETR);
  29         /* GPIO configuration for EVAL board
  30          * => Uart4 TX = G11
  31          */
  32         writel(0xffbfffff, GPIOG_BASE + 0x00);
  33         writel(0x00006000, GPIOG_BASE + 0x24);
  34 #else
  35
  36 #error("CONFIG_DEBUG_UART_BASE: not supported value")
  37
  38 #endif
  39 }
  40 #endif
  41
  42 #ifdef CONFIG_PMIC_STPMIC1
  43 int board_ddr_power_init(enum ddr_type ddr_type)
  44 {
  45         struct udevice *dev;
  46         bool buck3_at_1800000v = false;
  47         int ret;
  48         u32 buck2;
  49
  50         ret = uclass_get_device_by_driver(UCLASS_PMIC,
  51                                           DM_GET_DRIVER(pmic_stpmic1), &dev);
  52         if (ret)
  53                 /* No PMIC on board */
  54                 return 0;
  55
  56         switch (ddr_type) {
  57         case STM32MP_DDR3:
  58                 /* VTT = Set LDO3 to sync mode */
  59                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
  60                 if (ret < 0)
  61                         return ret;
  62
  63                 ret &= ~STPMIC1_LDO3_MODE;
  64                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
  65                 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
  66
  67                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  68                                      ret);
  69                 if (ret < 0)
  70                         return ret;
  71
  72                 /* VDD_DDR = Set BUCK2 to 1.35V */
  73                 ret = pmic_clrsetbits(dev,
  74                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  75                                       STPMIC1_BUCK_VOUT_MASK,
  76                                       STPMIC1_BUCK2_1350000V);
  77                 if (ret < 0)
  78                         return ret;
  79
  80                 /* Enable VDD_DDR = BUCK2 */
  81                 ret = pmic_clrsetbits(dev,
  82                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  83                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
  84                 if (ret < 0)
  85                         return ret;
  86
  87                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  88
  89                 /* Enable VREF */
  90                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
  91                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
  92                 if (ret < 0)
  93                         return ret;
  94
  95                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  96
  97                 /* Enable VTT = LDO3 */
  98                 ret = pmic_clrsetbits(dev,
  99                                       STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 100                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 101                 if (ret < 0)
 102                         return ret;
 103
 104                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 105
 106                 break;
 107
 108         case STM32MP_LPDDR2_16:
 109         case STM32MP_LPDDR2_32:
 110         case STM32MP_LPDDR3_16:
 111         case STM32MP_LPDDR3_32:
 112                 /*
 113                  * configure VDD_DDR1 = LDO3
 114                  * Set LDO3 to 1.8V
 115                  * + bypass mode if BUCK3 = 1.8V
 116                  * + normal mode if BUCK3 != 1.8V
 117                  */
 118                 ret = pmic_reg_read(dev,
 119                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
 120                 if (ret < 0)
 121                         return ret;
 122
 123                 if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
 124                         buck3_at_1800000v = true;
 125
 126                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
 127                 if (ret < 0)
 128                         return ret;
 129
 130                 ret &= ~STPMIC1_LDO3_MODE;
 131                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
 132                 ret |= STPMIC1_LDO3_1800000;
 133                 if (buck3_at_1800000v)
 134                         ret |= STPMIC1_LDO3_MODE;
 135
 136                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 137                                      ret);
 138                 if (ret < 0)
 139                         return ret;
 140
 141                 /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
 142                 switch (ddr_type) {
 143                 case STM32MP_LPDDR2_32:
 144                 case STM32MP_LPDDR3_32:
 145                         buck2 = STPMIC1_BUCK2_1250000V;
 146                         break;
 147                 default:
 148                 case STM32MP_LPDDR2_16:
 149                 case STM32MP_LPDDR3_16:
 150                         buck2 = STPMIC1_BUCK2_1200000V;
 151                         break;
 152                 }
 153
 154                 ret = pmic_clrsetbits(dev,
 155                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 156                                       STPMIC1_BUCK_VOUT_MASK,
 157                                       buck2);
 158                 if (ret < 0)
 159                         return ret;
 160
 161                 /* Enable VDD_DDR1 = LDO3 */
 162                 ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 163                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 164                 if (ret < 0)
 165                         return ret;
 166
 167                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 168
 169                 /* Enable VDD_DDR2 =BUCK2 */
 170                 ret = pmic_clrsetbits(dev,
 171                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 172                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
 173                 if (ret < 0)
 174                         return ret;
 175
 176                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 177
 178                 /* Enable VREF */
 179                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
 180                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
 181                 if (ret < 0)
 182                         return ret;
 183
 184                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 185
 186                 break;
 187
 188         default:
 189                 break;
 190         };
 191
 192         return 0;
 193 }
 194 #endif