1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
9 #include <asm/arch/ddr.h>
10 #include <power/pmic.h>
11 #include <power/stpmic1.h>
13 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
14 void board_debug_uart_init(void)
16 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
19 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
21 /* UART4 clock enable */
22 setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
24 #define GPIOG_BASE 0x50008000
25 /* GPIOG clock enable */
26 writel(BIT(6), RCC_MP_AHB4ENSETR);
27 /* GPIO configuration for EVAL board
30 writel(0xffbfffff, GPIOG_BASE + 0x00);
31 writel(0x00006000, GPIOG_BASE + 0x24);
34 #error("CONFIG_DEBUG_UART_BASE: not supported value")
40 #ifdef CONFIG_PMIC_STPMIC1
41 int board_ddr_power_init(void)
46 ret = uclass_get_device_by_driver(UCLASS_PMIC,
47 DM_GET_DRIVER(pmic_stpmic1), &dev);
49 /* No PMIC on board */
52 /* VTT = Set LDO3 to sync mode */
53 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
57 ret &= ~STPMIC1_LDO3_MODE;
58 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
59 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
61 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
66 /* VDD_DDR = Set BUCK2 to 1.35V */
67 ret = pmic_clrsetbits(dev,
68 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
69 STPMIC1_BUCK_VOUT_MASK,
70 STPMIC1_BUCK2_1350000V);
74 /* Enable VDD_DDR = BUCK2 */
75 ret = pmic_clrsetbits(dev,
76 STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
77 STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
81 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
84 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
85 STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
89 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
92 ret = pmic_clrsetbits(dev,
93 STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
94 STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
98 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);