board/spear/x600/x600.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  *
   6  * Copyright (C) 2012 Stefan Roese <sr@denx.de>
   7  */
   8
   9 #include <common.h>
  10 #include <flash.h>
  11 #include <init.h>
  12 #include <micrel.h>
  13 #include <nand.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <phy.h>
  17 #include <rtc.h>
  18 #include <asm/io.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/spr_defs.h>
  22 #include <asm/arch/spr_misc.h>
  23 #include <linux/mtd/fsmc_nand.h>
  24 #include "fpga.h"
  25
  26 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  27
  28 int board_init(void)
  29 {
  30         /*
  31          * X600 is equipped with an M41T82 RTC. This RTC has the
  32          * HT bit (Halt Update), which needs to be cleared upon
  33          * power-up. Otherwise the RTC is halted.
  34          */
  35         rtc_reset();
  36
  37         return spear_board_init(MACH_TYPE_SPEAR600);
  38 }
  39
  40 int board_late_init(void)
  41 {
  42         /*
  43          * Monitor and env protection on by default
  44          */
  45         flash_protect(FLAG_PROTECT_SET,
  46                       CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
  47                       CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
  48                       2 * CONFIG_ENV_SECT_SIZE - 1,
  49                       &flash_info[0]);
  50
  51         /* Init FPGA subsystem */
  52         x600_init_fpga();
  53
  54         return 0;
  55 }
  56
  57 /*
  58  * board_nand_init - Board specific NAND initialization
  59  * @nand:       mtd private chip structure
  60  *
  61  * Called by nand_init_chip to initialize the board specific functions
  62  */
  63
  64 void board_nand_init(void)
  65 {
  66         struct misc_regs *const misc_regs_p =
  67                 (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  68         struct nand_chip *nand = &nand_chip[0];
  69
  70         if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
  71                 fsmc_nand_init(nand);
  72 }
  73
  74 int board_phy_config(struct phy_device *phydev)
  75 {
  76         unsigned short id1, id2;
  77
  78         /* check whether KSZ9031 or AR8035 has to be configured */
  79         id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  80         id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  81
  82         if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  83                 /* PHY configuration for Micrel KSZ9031 */
  84                 printf("PHY KSZ9031 detected - ");
  85
  86                 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  87
  88                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
  89                 ksz9031_phy_extended_write(phydev, 0x02,
  90                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  91                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  92                                            0x0000);
  93                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  94                 ksz9031_phy_extended_write(phydev, 0x02,
  95                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  96                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  97                                            0x0000);
  98                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  99                 ksz9031_phy_extended_write(phydev, 0x02,
 100                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 101                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 102                                            0x0000);
 103                 /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
 104                 ksz9031_phy_extended_write(phydev, 0x02,
 105                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 106                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 107                                            0x03FF);
 108         } else {
 109                 /* PHY configuration for Vitesse VSC8641 */
 110                 printf("PHY VSC8641 detected - ");
 111
 112                 /* Extended PHY control 1, select GMII */
 113                 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
 114
 115                 /* Software reset necessary after GMII mode selction */
 116                 phy_reset(phydev);
 117
 118                 /* Enable extended page register access */
 119                 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
 120
 121                 /* 17e: Enhanced LED behavior, needs to be written twice */
 122                 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
 123                 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
 124
 125                 /* 16e: Enhanced LED method select */
 126                 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
 127
 128                 /* Disable extended page register access */
 129                 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
 130
 131                 /* Enable clock output pin */
 132                 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
 133         }
 134
 135         if (phydev->drv->config)
 136                 phydev->drv->config(phydev);
 137
 138         return 0;
 139 }
 140
 141 int board_eth_init(bd_t *bis)
 142 {
 143         int ret = 0;
 144
 145         if (designware_initialize(CONFIG_SPEAR_ETHBASE,
 146                                   PHY_INTERFACE_MODE_GMII) >= 0)
 147                 ret++;
 148
 149         return ret;
 150 }