board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   7  *
   8  * Based on SPL code from Solidrun tree, which is:
   9  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  10  *
  11  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  12  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/imx-common/iomux-v3.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <spl.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  51
  52 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  53
  54 int dram_init(void)
  55 {
  56         gd->ram_size = imx_ddr_size();
  57         return 0;
  58 }
  59
  60 static iomux_v3_cfg_t const uart1_pads[] = {
  61         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  62         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  63 };
  64
  65 static iomux_v3_cfg_t const usdhc2_pads[] = {
  66         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72 };
  73
  74 static void setup_iomux_uart(void)
  75 {
  76         SETUP_IOMUX_PADS(uart1_pads);
  77 }
  78
  79 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  80         {USDHC2_BASE_ADDR},
  81 };
  82
  83 int board_mmc_getcd(struct mmc *mmc)
  84 {
  85         return 1; /* uSDHC2 is always present */
  86 }
  87
  88 int board_mmc_init(bd_t *bis)
  89 {
  90         SETUP_IOMUX_PADS(usdhc2_pads);
  91         usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  92         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  93         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  94
  95         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  96 }
  97
  98 static iomux_v3_cfg_t const enet_pads[] = {
  99         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101         /* AR8035 reset */
 102         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 103         /* AR8035 interrupt */
 104         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 105         /* GPIO16 -> AR8035 25MHz */
 106         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 107         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 108         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 109         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 110         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 111         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 112         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 113         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 114         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 115         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 116         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 117         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 118         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 119         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 120         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 121 };
 122
 123 static void setup_iomux_enet(void)
 124 {
 125         SETUP_IOMUX_PADS(enet_pads);
 126
 127         gpio_direction_output(ETH_PHY_RESET, 0);
 128         mdelay(2);
 129         gpio_set_value(ETH_PHY_RESET, 1);
 130 }
 131
 132 int board_phy_config(struct phy_device *phydev)
 133 {
 134         if (phydev->drv->config)
 135                 phydev->drv->config(phydev);
 136
 137         return 0;
 138 }
 139
 140 int board_eth_init(bd_t *bis)
 141 {
 142         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 143
 144         int ret = enable_fec_anatop_clock(ENET_25MHZ);
 145         if (ret)
 146                 return ret;
 147
 148         /* set gpr1[ENET_CLK_SEL] */
 149         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 150
 151         setup_iomux_enet();
 152
 153         return cpu_eth_init(bis);
 154 }
 155
 156 int board_early_init_f(void)
 157 {
 158         setup_iomux_uart();
 159         return 0;
 160 }
 161
 162 int board_init(void)
 163 {
 164         /* address of boot parameters */
 165         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 166
 167         return 0;
 168 }
 169
 170 int checkboard(void)
 171 {
 172         puts("Board: MX6 Hummingboard\n");
 173         return 0;
 174 }
 175
 176 #ifdef CONFIG_SPL_BUILD
 177 #include <asm/arch/mx6-ddr.h>
 178 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 179         .dram_sdclk_0 =  0x00020030,
 180         .dram_sdclk_1 =  0x00020030,
 181         .dram_cas =  0x00020030,
 182         .dram_ras =  0x00020030,
 183         .dram_reset =  0x00020030,
 184         .dram_sdcke0 =  0x00003000,
 185         .dram_sdcke1 =  0x00003000,
 186         .dram_sdba2 =  0x00000000,
 187         .dram_sdodt0 =  0x00003030,
 188         .dram_sdodt1 =  0x00003030,
 189         .dram_sdqs0 =  0x00000030,
 190         .dram_sdqs1 =  0x00000030,
 191         .dram_sdqs2 =  0x00000030,
 192         .dram_sdqs3 =  0x00000030,
 193         .dram_sdqs4 =  0x00000030,
 194         .dram_sdqs5 =  0x00000030,
 195         .dram_sdqs6 =  0x00000030,
 196         .dram_sdqs7 =  0x00000030,
 197         .dram_dqm0 =  0x00020030,
 198         .dram_dqm1 =  0x00020030,
 199         .dram_dqm2 =  0x00020030,
 200         .dram_dqm3 =  0x00020030,
 201         .dram_dqm4 =  0x00020030,
 202         .dram_dqm5 =  0x00020030,
 203         .dram_dqm6 =  0x00020030,
 204         .dram_dqm7 =  0x00020030,
 205 };
 206
 207 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 208         .dram_sdclk_0 = 0x00000028,
 209         .dram_sdclk_1 = 0x00000028,
 210         .dram_cas =     0x00000028,
 211         .dram_ras =     0x00000028,
 212         .dram_reset =   0x000c0028,
 213         .dram_sdcke0 =  0x00003000,
 214         .dram_sdcke1 =  0x00003000,
 215         .dram_sdba2 =   0x00000000,
 216         .dram_sdodt0 =  0x00003030,
 217         .dram_sdodt1 =  0x00003030,
 218         .dram_sdqs0 =   0x00000028,
 219         .dram_sdqs1 =   0x00000028,
 220         .dram_sdqs2 =   0x00000028,
 221         .dram_sdqs3 =   0x00000028,
 222         .dram_sdqs4 =   0x00000028,
 223         .dram_sdqs5 =   0x00000028,
 224         .dram_sdqs6 =   0x00000028,
 225         .dram_sdqs7 =   0x00000028,
 226         .dram_dqm0 =    0x00000028,
 227         .dram_dqm1 =    0x00000028,
 228         .dram_dqm2 =    0x00000028,
 229         .dram_dqm3 =    0x00000028,
 230         .dram_dqm4 =    0x00000028,
 231         .dram_dqm5 =    0x00000028,
 232         .dram_dqm6 =    0x00000028,
 233         .dram_dqm7 =    0x00000028,
 234 };
 235
 236 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 237         .grp_ddr_type =  0x000C0000,
 238         .grp_ddrmode_ctl =  0x00020000,
 239         .grp_ddrpke =  0x00000000,
 240         .grp_addds =  0x00000030,
 241         .grp_ctlds =  0x00000030,
 242         .grp_ddrmode =  0x00020000,
 243         .grp_b0ds =  0x00000030,
 244         .grp_b1ds =  0x00000030,
 245         .grp_b2ds =  0x00000030,
 246         .grp_b3ds =  0x00000030,
 247         .grp_b4ds =  0x00000030,
 248         .grp_b5ds =  0x00000030,
 249         .grp_b6ds =  0x00000030,
 250         .grp_b7ds =  0x00000030,
 251 };
 252
 253 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 254         .grp_ddr_type = 0x000c0000,
 255         .grp_ddrmode_ctl = 0x00020000,
 256         .grp_ddrpke = 0x00000000,
 257         .grp_addds = 0x00000028,
 258         .grp_ctlds = 0x00000028,
 259         .grp_ddrmode = 0x00020000,
 260         .grp_b0ds = 0x00000028,
 261         .grp_b1ds = 0x00000028,
 262         .grp_b2ds = 0x00000028,
 263         .grp_b3ds = 0x00000028,
 264         .grp_b4ds = 0x00000028,
 265         .grp_b5ds = 0x00000028,
 266         .grp_b6ds = 0x00000028,
 267         .grp_b7ds = 0x00000028,
 268 };
 269
 270 /* microSOM with Dual processor and 1GB memory */
 271 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 272         .p0_mpwldectrl0 =  0x00000000,
 273         .p0_mpwldectrl1 =  0x00000000,
 274         .p1_mpwldectrl0 =  0x00000000,
 275         .p1_mpwldectrl1 =  0x00000000,
 276         .p0_mpdgctrl0 =    0x0314031c,
 277         .p0_mpdgctrl1 =    0x023e0304,
 278         .p1_mpdgctrl0 =    0x03240330,
 279         .p1_mpdgctrl1 =    0x03180260,
 280         .p0_mprddlctl =    0x3630323c,
 281         .p1_mprddlctl =    0x3436283a,
 282         .p0_mpwrdlctl =    0x36344038,
 283         .p1_mpwrdlctl =    0x422a423c,
 284 };
 285
 286 /* microSOM with Quad processor and 2GB memory */
 287 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 288         .p0_mpwldectrl0 =  0x00000000,
 289         .p0_mpwldectrl1 =  0x00000000,
 290         .p1_mpwldectrl0 =  0x00000000,
 291         .p1_mpwldectrl1 =  0x00000000,
 292         .p0_mpdgctrl0 =    0x0314031c,
 293         .p0_mpdgctrl1 =    0x023e0304,
 294         .p1_mpdgctrl0 =    0x03240330,
 295         .p1_mpdgctrl1 =    0x03180260,
 296         .p0_mprddlctl =    0x3630323c,
 297         .p1_mprddlctl =    0x3436283a,
 298         .p0_mpwrdlctl =    0x36344038,
 299         .p1_mpwrdlctl =    0x422a423c,
 300 };
 301
 302 /* microSOM with Solo processor and 512MB memory */
 303 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 304         .p0_mpwldectrl0 = 0x0045004D,
 305         .p0_mpwldectrl1 = 0x003A0047,
 306         .p0_mpdgctrl0 =   0x023C0224,
 307         .p0_mpdgctrl1 =   0x02000220,
 308         .p0_mprddlctl =   0x44444846,
 309         .p0_mpwrdlctl =   0x32343032,
 310 };
 311
 312 /* microSOM with Dual lite processor and 1GB memory */
 313 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 314         .p0_mpwldectrl0 =  0x0045004D,
 315         .p0_mpwldectrl1 =  0x003A0047,
 316         .p1_mpwldectrl0 =  0x001F001F,
 317         .p1_mpwldectrl1 =  0x00210035,
 318         .p0_mpdgctrl0 =    0x023C0224,
 319         .p0_mpdgctrl1 =    0x02000220,
 320         .p1_mpdgctrl0 =    0x02200220,
 321         .p1_mpdgctrl1 =    0x02000220,
 322         .p0_mprddlctl =    0x44444846,
 323         .p1_mprddlctl =    0x4042463C,
 324         .p0_mpwrdlctl =    0x32343032,
 325         .p1_mpwrdlctl =    0x36363430,
 326 };
 327
 328 static struct mx6_ddr3_cfg mem_ddr_2g = {
 329         .mem_speed = 1600,
 330         .density   = 2,
 331         .width     = 16,
 332         .banks     = 8,
 333         .rowaddr   = 14,
 334         .coladdr   = 10,
 335         .pagesz    = 2,
 336         .trcd      = 1375,
 337         .trcmin    = 4875,
 338         .trasmin   = 3500,
 339         .SRT       = 1,
 340 };
 341
 342 static struct mx6_ddr3_cfg mem_ddr_4g = {
 343         .mem_speed = 1600,
 344         .density = 4,
 345         .width = 16,
 346         .banks = 8,
 347         .rowaddr = 15,
 348         .coladdr = 10,
 349         .pagesz = 2,
 350         .trcd = 1375,
 351         .trcmin = 4875,
 352         .trasmin = 3500,
 353 };
 354
 355 static void ccgr_init(void)
 356 {
 357         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 358
 359         writel(0x00C03F3F, &ccm->CCGR0);
 360         writel(0x0030FC03, &ccm->CCGR1);
 361         writel(0x0FFFC000, &ccm->CCGR2);
 362         writel(0x3FF00000, &ccm->CCGR3);
 363         writel(0x00FFF300, &ccm->CCGR4);
 364         writel(0x0F0000C3, &ccm->CCGR5);
 365         writel(0x000003FF, &ccm->CCGR6);
 366 }
 367
 368 static void gpr_init(void)
 369 {
 370         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 371
 372         /* enable AXI cache for VDOA/VPU/IPU */
 373         writel(0xF00000CF, &iomux->gpr[4]);
 374         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 375         writel(0x007F007F, &iomux->gpr[6]);
 376         writel(0x007F007F, &iomux->gpr[7]);
 377 }
 378
 379 /*
 380  * This section requires the differentiation between Solidrun mx6 boards, but
 381  * for now, it will configure only for the mx6dual hummingboard version.
 382  */
 383 static void spl_dram_init(int width)
 384 {
 385         struct mx6_ddr_sysinfo sysinfo = {
 386                 /* width of data bus: 0=16, 1=32, 2=64 */
 387                 .dsize = width / 32,
 388                 /* config for full 4GB range so that get_mem_size() works */
 389                 .cs_density = 32,       /* 32Gb per CS */
 390                 .ncs = 1,               /* single chip select */
 391                 .cs1_mirror = 0,
 392                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 393                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 394                 .walat = 1,     /* Write additional latency */
 395                 .ralat = 5,     /* Read additional latency */
 396                 .mif3_mode = 3, /* Command prediction working mode */
 397                 .bi_on = 1,     /* Bank interleaving enabled */
 398                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 399                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 400         };
 401
 402         if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
 403                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 404         else
 405                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 406
 407         if (is_cpu_type(MXC_CPU_MX6D))
 408                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 409         else if (is_cpu_type(MXC_CPU_MX6Q))
 410                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 411         else if (is_cpu_type(MXC_CPU_MX6DL))
 412                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 413         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 414                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 415 }
 416
 417 void board_init_f(ulong dummy)
 418 {
 419         /* setup AIPS and disable watchdog */
 420         arch_cpu_init();
 421
 422         ccgr_init();
 423         gpr_init();
 424
 425         /* iomux and setup of i2c */
 426         board_early_init_f();
 427
 428         /* setup GP timer */
 429         timer_init();
 430
 431         /* UART clocks enabled and gd valid - init serial console */
 432         preloader_console_init();
 433
 434         /* DDR initialization */
 435         if (is_cpu_type(MXC_CPU_MX6SOLO))
 436                 spl_dram_init(32);
 437         else
 438                 spl_dram_init(64);
 439
 440         /* Clear the BSS. */
 441         memset(__bss_start, 0, __bss_end - __bss_start);
 442
 443         /* load/boot image from boot device */
 444         board_init_r(NULL, 0);
 445 }
 446 #endif