board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   8  *
   9  * Based on SPL code from Solidrun tree, which is:
  10  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11  *
  12  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14  */
  15
  16 #include <init.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <env.h>
  23 #include <linux/errno.h>
  24 #include <asm/gpio.h>
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/sata.h>
  27 #include <asm/mach-imx/video.h>
  28 #include <mmc.h>
  29 #include <fsl_esdhc_imx.h>
  30 #include <malloc.h>
  31 #include <miiphy.h>
  32 #include <netdev.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/sys_proto.h>
  36 #include <spl.h>
  37 #include <usb.h>
  38 #include <usb/ehci-ci.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  47         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52
  53 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58
  59 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  60 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  61
  62 enum board_type {
  63         CUBOXI          = 0x00,
  64         HUMMINGBOARD    = 0x01,
  65         HUMMINGBOARD2   = 0x02,
  66         UNKNOWN         = 0x03,
  67 };
  68
  69 #define MEM_STRIDE 0x4000000
  70 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  71 {
  72         volatile u32 *addr;
  73         u32          save[64];
  74         u32          cnt;
  75         u32          size;
  76         int          i = 0;
  77
  78         /* First save the data */
  79         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  80                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  81                 sync ();
  82                 save[i++] = *addr;
  83                 sync ();
  84         }
  85
  86         /* First write a signature */
  87         * (volatile u32 *)base = 0x12345678;
  88         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  89                 * (volatile u32 *)((u32)base + size) = size;
  90                 sync ();
  91                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  92                         break;
  93                 }
  94         }
  95
  96         /* Restore the data */
  97         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
  98                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  99                 sync ();
 100                 *addr = save[i--];
 101                 sync ();
 102         }
 103
 104         return (size);
 105 }
 106
 107 int dram_init(void)
 108 {
 109         u32 max_size = imx_ddr_size();
 110
 111         gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
 112                                                 (u32)max_size);
 113
 114         return 0;
 115 }
 116
 117 static iomux_v3_cfg_t const uart1_pads[] = {
 118         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 119         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 120 };
 121
 122 static iomux_v3_cfg_t const usdhc2_pads[] = {
 123         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129 };
 130
 131 static iomux_v3_cfg_t const usdhc3_pads[] = {
 132         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143 };
 144
 145 static iomux_v3_cfg_t const board_detect[] = {
 146         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 147         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 148         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 149         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 150 };
 151
 152 static iomux_v3_cfg_t const som_rev_detect[] = {
 153         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 154         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 155         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 156 };
 157
 158 static iomux_v3_cfg_t const usb_pads[] = {
 159         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 160 };
 161
 162 static void setup_iomux_uart(void)
 163 {
 164         SETUP_IOMUX_PADS(uart1_pads);
 165 }
 166
 167 static struct fsl_esdhc_cfg usdhc_cfg = {
 168         .esdhc_base = USDHC2_BASE_ADDR,
 169         .max_bus_width = 4,
 170 };
 171
 172 static struct fsl_esdhc_cfg emmc_cfg = {
 173         .esdhc_base = USDHC3_BASE_ADDR,
 174         .max_bus_width = 8,
 175 };
 176
 177 int board_mmc_get_env_dev(int devno)
 178 {
 179         return devno - 1;
 180 }
 181
 182 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 183
 184 int board_mmc_getcd(struct mmc *mmc)
 185 {
 186         struct fsl_esdhc_cfg *cfg = mmc->priv;
 187         int ret = 0;
 188
 189         switch (cfg->esdhc_base) {
 190         case USDHC2_BASE_ADDR:
 191                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 192                 break;
 193         case USDHC3_BASE_ADDR:
 194                 ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
 195                 break;
 196         }
 197
 198         return ret;
 199 }
 200
 201 static int mmc_init_main(bd_t *bis)
 202 {
 203         int ret;
 204
 205         /*
 206          * Following map is done:
 207          * (U-Boot device node)    (Physical Port)
 208          * mmc0                    Carrier board MicroSD
 209          * mmc1                    SOM eMMC
 210          */
 211         SETUP_IOMUX_PADS(usdhc2_pads);
 212         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 213         ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
 214         if (ret)
 215                 return ret;
 216
 217         SETUP_IOMUX_PADS(usdhc3_pads);
 218         emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 219         return fsl_esdhc_initialize(bis, &emmc_cfg);
 220 }
 221
 222 static int mmc_init_spl(bd_t *bis)
 223 {
 224         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 225         unsigned reg = readl(&psrc->sbmr1) >> 11;
 226
 227         /*
 228          * Upon reading BOOT_CFG register the following map is done:
 229          * Bit 11 and 12 of BOOT_CFG register can determine the current
 230          * mmc port
 231          * 0x1                  SD2
 232          * 0x2                  SD3
 233          */
 234         switch (reg & 0x3) {
 235         case 0x1:
 236                 SETUP_IOMUX_PADS(usdhc2_pads);
 237                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 238                 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 239                 return fsl_esdhc_initialize(bis, &usdhc_cfg);
 240         case 0x2:
 241                 SETUP_IOMUX_PADS(usdhc3_pads);
 242                 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 243                 gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
 244                 return fsl_esdhc_initialize(bis, &emmc_cfg);
 245         }
 246
 247         return -ENODEV;
 248 }
 249
 250 int board_mmc_init(bd_t *bis)
 251 {
 252         if (IS_ENABLED(CONFIG_SPL_BUILD))
 253                 return mmc_init_spl(bis);
 254
 255         return mmc_init_main(bis);
 256 }
 257
 258 static iomux_v3_cfg_t const enet_pads[] = {
 259         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 260         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 261         /* AR8035 reset */
 262         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 263         /* AR8035 interrupt */
 264         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 265         /* GPIO16 -> AR8035 25MHz */
 266         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 267         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 268         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 269         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 270         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 271         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 272         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 273         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 274         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 275         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 276         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 277         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 278         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 279         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 280         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 281         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 282         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 283 };
 284
 285 static void setup_iomux_enet(void)
 286 {
 287         SETUP_IOMUX_PADS(enet_pads);
 288
 289         gpio_direction_output(ETH_PHY_RESET, 0);
 290         mdelay(10);
 291         gpio_set_value(ETH_PHY_RESET, 1);
 292         udelay(100);
 293 }
 294
 295 int board_phy_config(struct phy_device *phydev)
 296 {
 297         if (phydev->drv->config)
 298                 phydev->drv->config(phydev);
 299
 300         return 0;
 301 }
 302
 303 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 304 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 305
 306 int board_eth_init(bd_t *bis)
 307 {
 308         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 309         struct mii_dev *bus;
 310         struct phy_device *phydev;
 311
 312         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 313         if (ret)
 314                 return ret;
 315
 316         /* set gpr1[ENET_CLK_SEL] */
 317         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 318
 319         setup_iomux_enet();
 320
 321         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 322         if (!bus)
 323                 return -EINVAL;
 324
 325         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 326         if (!phydev) {
 327                 ret = -EINVAL;
 328                 goto free_bus;
 329         }
 330
 331         debug("using phy at address %d\n", phydev->addr);
 332         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 333         if (ret)
 334                 goto free_phydev;
 335
 336         return 0;
 337
 338 free_phydev:
 339         free(phydev);
 340 free_bus:
 341         free(bus);
 342         return ret;
 343 }
 344
 345 #ifdef CONFIG_VIDEO_IPUV3
 346 static void do_enable_hdmi(struct display_info_t const *dev)
 347 {
 348         imx_enable_hdmi_phy();
 349 }
 350
 351 struct display_info_t const displays[] = {
 352         {
 353                 .bus    = -1,
 354                 .addr   = 0,
 355                 .pixfmt = IPU_PIX_FMT_RGB24,
 356                 .detect = detect_hdmi,
 357                 .enable = do_enable_hdmi,
 358                 .mode   = {
 359                         .name           = "HDMI",
 360                         /* 1024x768@60Hz (VESA)*/
 361                         .refresh        = 60,
 362                         .xres           = 1024,
 363                         .yres           = 768,
 364                         .pixclock       = 15384,
 365                         .left_margin    = 160,
 366                         .right_margin   = 24,
 367                         .upper_margin   = 29,
 368                         .lower_margin   = 3,
 369                         .hsync_len      = 136,
 370                         .vsync_len      = 6,
 371                         .sync           = FB_SYNC_EXT,
 372                         .vmode          = FB_VMODE_NONINTERLACED
 373                 }
 374         }
 375 };
 376
 377 size_t display_count = ARRAY_SIZE(displays);
 378
 379 static int setup_display(void)
 380 {
 381         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 382         int reg;
 383         int timeout = 100000;
 384
 385         enable_ipu_clock();
 386         imx_setup_hdmi();
 387
 388         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 389         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 390
 391         reg = readl(&ccm->analog_pll_video);
 392         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 393         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 394         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 395         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 396         writel(reg, &ccm->analog_pll_video);
 397
 398         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 399         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 400
 401         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 402         writel(reg, &ccm->analog_pll_video);
 403
 404         while (timeout--)
 405                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 406                         break;
 407         if (timeout < 0) {
 408                 printf("Warning: video pll lock timeout!\n");
 409                 return -ETIMEDOUT;
 410         }
 411
 412         reg = readl(&ccm->analog_pll_video);
 413         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 414         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 415         writel(reg, &ccm->analog_pll_video);
 416
 417         /* gate ipu1_di0_clk */
 418         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 419
 420         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 421         reg = readl(&ccm->chsccdr);
 422         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 423                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 424                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 425         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 426                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 427                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 428         writel(reg, &ccm->chsccdr);
 429
 430         /* enable ipu1_di0_clk */
 431         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 432
 433         return 0;
 434 }
 435 #endif /* CONFIG_VIDEO_IPUV3 */
 436
 437 #ifdef CONFIG_USB_EHCI_MX6
 438 static void setup_usb(void)
 439 {
 440         SETUP_IOMUX_PADS(usb_pads);
 441 }
 442
 443 int board_ehci_hcd_init(int port)
 444 {
 445         if (port == 1)
 446                 gpio_direction_output(USB_H1_VBUS, 1);
 447
 448         return 0;
 449 }
 450 #endif
 451
 452 int board_early_init_f(void)
 453 {
 454         setup_iomux_uart();
 455
 456 #ifdef CONFIG_CMD_SATA
 457         setup_sata();
 458 #endif
 459
 460 #ifdef CONFIG_USB_EHCI_MX6
 461         setup_usb();
 462 #endif
 463         return 0;
 464 }
 465
 466 int board_init(void)
 467 {
 468         int ret = 0;
 469
 470         /* address of boot parameters */
 471         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 472
 473 #ifdef CONFIG_VIDEO_IPUV3
 474         ret = setup_display();
 475 #endif
 476
 477         return ret;
 478 }
 479
 480 static enum board_type board_type(void)
 481 {
 482         int val1, val2, val3;
 483
 484         SETUP_IOMUX_PADS(board_detect);
 485
 486         /*
 487          * Machine selection -
 488          * Machine      val1, val2, val3
 489          * ----------------------------
 490          * HB2            x     x    0
 491          * HB rev 3.x     x     0    x
 492          * CBi            0     1    x
 493          * HB             1     1    x
 494          */
 495
 496         gpio_direction_input(IMX_GPIO_NR(2, 8));
 497         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 498
 499         if (val3 == 0)
 500                 return HUMMINGBOARD2;
 501
 502         gpio_direction_input(IMX_GPIO_NR(3, 4));
 503         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 504
 505         if (val2 == 0)
 506                 return HUMMINGBOARD;
 507
 508         gpio_direction_input(IMX_GPIO_NR(4, 9));
 509         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 510
 511         if (val1 == 0) {
 512                 return CUBOXI;
 513         } else {
 514                 return HUMMINGBOARD;
 515         }
 516 }
 517
 518 static bool is_rev_15_som(void)
 519 {
 520         int val1, val2;
 521         SETUP_IOMUX_PADS(som_rev_detect);
 522
 523         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 524         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 525
 526         if (val1 == 1 && val2 == 0)
 527                 return true;
 528
 529         return false;
 530 }
 531
 532 static bool has_emmc(void)
 533 {
 534         struct mmc *mmc;
 535         mmc = find_mmc_device(1);
 536         if (!mmc)
 537                 return 0;
 538         return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
 539 }
 540
 541 int checkboard(void)
 542 {
 543         switch (board_type()) {
 544         case CUBOXI:
 545                 puts("Board: MX6 Cubox-i");
 546                 break;
 547         case HUMMINGBOARD:
 548                 puts("Board: MX6 HummingBoard");
 549                 break;
 550         case HUMMINGBOARD2:
 551                 puts("Board: MX6 HummingBoard2");
 552                 break;
 553         case UNKNOWN:
 554         default:
 555                 puts("Board: Unknown\n");
 556                 goto out;
 557         }
 558
 559         if (is_rev_15_som())
 560                 puts(" (som rev 1.5)\n");
 561         else
 562                 puts("\n");
 563
 564 out:
 565         return 0;
 566 }
 567
 568 int board_late_init(void)
 569 {
 570 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 571         switch (board_type()) {
 572         case CUBOXI:
 573                 env_set("board_name", "CUBOXI");
 574                 break;
 575         case HUMMINGBOARD:
 576                 env_set("board_name", "HUMMINGBOARD");
 577                 break;
 578         case HUMMINGBOARD2:
 579                 env_set("board_name", "HUMMINGBOARD2");
 580                 break;
 581         case UNKNOWN:
 582         default:
 583                 env_set("board_name", "CUBOXI");
 584         }
 585
 586         if (is_mx6dq())
 587                 env_set("board_rev", "MX6Q");
 588         else
 589                 env_set("board_rev", "MX6DL");
 590
 591         if (is_rev_15_som())
 592                 env_set("som_rev", "V15");
 593
 594         if (has_emmc())
 595                 env_set("has_emmc", "yes");
 596
 597 #endif
 598
 599         return 0;
 600 }
 601
 602 #ifdef CONFIG_SPL_BUILD
 603 #include <asm/arch/mx6-ddr.h>
 604 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 605         .dram_sdclk_0 =  0x00020030,
 606         .dram_sdclk_1 =  0x00020030,
 607         .dram_cas =  0x00020030,
 608         .dram_ras =  0x00020030,
 609         .dram_reset =  0x000c0030,
 610         .dram_sdcke0 =  0x00003000,
 611         .dram_sdcke1 =  0x00003000,
 612         .dram_sdba2 =  0x00000000,
 613         .dram_sdodt0 =  0x00003030,
 614         .dram_sdodt1 =  0x00003030,
 615         .dram_sdqs0 =  0x00000030,
 616         .dram_sdqs1 =  0x00000030,
 617         .dram_sdqs2 =  0x00000030,
 618         .dram_sdqs3 =  0x00000030,
 619         .dram_sdqs4 =  0x00000030,
 620         .dram_sdqs5 =  0x00000030,
 621         .dram_sdqs6 =  0x00000030,
 622         .dram_sdqs7 =  0x00000030,
 623         .dram_dqm0 =  0x00020030,
 624         .dram_dqm1 =  0x00020030,
 625         .dram_dqm2 =  0x00020030,
 626         .dram_dqm3 =  0x00020030,
 627         .dram_dqm4 =  0x00020030,
 628         .dram_dqm5 =  0x00020030,
 629         .dram_dqm6 =  0x00020030,
 630         .dram_dqm7 =  0x00020030,
 631 };
 632
 633 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 634         .dram_sdclk_0 = 0x00000028,
 635         .dram_sdclk_1 = 0x00000028,
 636         .dram_cas =     0x00000028,
 637         .dram_ras =     0x00000028,
 638         .dram_reset =   0x000c0028,
 639         .dram_sdcke0 =  0x00003000,
 640         .dram_sdcke1 =  0x00003000,
 641         .dram_sdba2 =   0x00000000,
 642         .dram_sdodt0 =  0x00003030,
 643         .dram_sdodt1 =  0x00003030,
 644         .dram_sdqs0 =   0x00000028,
 645         .dram_sdqs1 =   0x00000028,
 646         .dram_sdqs2 =   0x00000028,
 647         .dram_sdqs3 =   0x00000028,
 648         .dram_sdqs4 =   0x00000028,
 649         .dram_sdqs5 =   0x00000028,
 650         .dram_sdqs6 =   0x00000028,
 651         .dram_sdqs7 =   0x00000028,
 652         .dram_dqm0 =    0x00000028,
 653         .dram_dqm1 =    0x00000028,
 654         .dram_dqm2 =    0x00000028,
 655         .dram_dqm3 =    0x00000028,
 656         .dram_dqm4 =    0x00000028,
 657         .dram_dqm5 =    0x00000028,
 658         .dram_dqm6 =    0x00000028,
 659         .dram_dqm7 =    0x00000028,
 660 };
 661
 662 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 663         .grp_ddr_type =  0x000C0000,
 664         .grp_ddrmode_ctl =  0x00020000,
 665         .grp_ddrpke =  0x00000000,
 666         .grp_addds =  0x00000030,
 667         .grp_ctlds =  0x00000030,
 668         .grp_ddrmode =  0x00020000,
 669         .grp_b0ds =  0x00000030,
 670         .grp_b1ds =  0x00000030,
 671         .grp_b2ds =  0x00000030,
 672         .grp_b3ds =  0x00000030,
 673         .grp_b4ds =  0x00000030,
 674         .grp_b5ds =  0x00000030,
 675         .grp_b6ds =  0x00000030,
 676         .grp_b7ds =  0x00000030,
 677 };
 678
 679 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 680         .grp_ddr_type = 0x000c0000,
 681         .grp_ddrmode_ctl = 0x00020000,
 682         .grp_ddrpke = 0x00000000,
 683         .grp_addds = 0x00000028,
 684         .grp_ctlds = 0x00000028,
 685         .grp_ddrmode = 0x00020000,
 686         .grp_b0ds = 0x00000028,
 687         .grp_b1ds = 0x00000028,
 688         .grp_b2ds = 0x00000028,
 689         .grp_b3ds = 0x00000028,
 690         .grp_b4ds = 0x00000028,
 691         .grp_b5ds = 0x00000028,
 692         .grp_b6ds = 0x00000028,
 693         .grp_b7ds = 0x00000028,
 694 };
 695
 696 /* microSOM with Dual processor and 1GB memory */
 697 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 698         .p0_mpwldectrl0 =  0x00000000,
 699         .p0_mpwldectrl1 =  0x00000000,
 700         .p1_mpwldectrl0 =  0x00000000,
 701         .p1_mpwldectrl1 =  0x00000000,
 702         .p0_mpdgctrl0 =    0x0314031c,
 703         .p0_mpdgctrl1 =    0x023e0304,
 704         .p1_mpdgctrl0 =    0x03240330,
 705         .p1_mpdgctrl1 =    0x03180260,
 706         .p0_mprddlctl =    0x3630323c,
 707         .p1_mprddlctl =    0x3436283a,
 708         .p0_mpwrdlctl =    0x36344038,
 709         .p1_mpwrdlctl =    0x422a423c,
 710 };
 711
 712 /* microSOM with Quad processor and 2GB memory */
 713 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 714         .p0_mpwldectrl0 =  0x00000000,
 715         .p0_mpwldectrl1 =  0x00000000,
 716         .p1_mpwldectrl0 =  0x00000000,
 717         .p1_mpwldectrl1 =  0x00000000,
 718         .p0_mpdgctrl0 =    0x0314031c,
 719         .p0_mpdgctrl1 =    0x023e0304,
 720         .p1_mpdgctrl0 =    0x03240330,
 721         .p1_mpdgctrl1 =    0x03180260,
 722         .p0_mprddlctl =    0x3630323c,
 723         .p1_mprddlctl =    0x3436283a,
 724         .p0_mpwrdlctl =    0x36344038,
 725         .p1_mpwrdlctl =    0x422a423c,
 726 };
 727
 728 /* microSOM with Solo processor and 512MB memory */
 729 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 730         .p0_mpwldectrl0 = 0x0045004D,
 731         .p0_mpwldectrl1 = 0x003A0047,
 732         .p0_mpdgctrl0 =   0x023C0224,
 733         .p0_mpdgctrl1 =   0x02000220,
 734         .p0_mprddlctl =   0x44444846,
 735         .p0_mpwrdlctl =   0x32343032,
 736 };
 737
 738 /* microSOM with Dual lite processor and 1GB memory */
 739 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 740         .p0_mpwldectrl0 =  0x0045004D,
 741         .p0_mpwldectrl1 =  0x003A0047,
 742         .p1_mpwldectrl0 =  0x001F001F,
 743         .p1_mpwldectrl1 =  0x00210035,
 744         .p0_mpdgctrl0 =    0x023C0224,
 745         .p0_mpdgctrl1 =    0x02000220,
 746         .p1_mpdgctrl0 =    0x02200220,
 747         .p1_mpdgctrl1 =    0x02040208,
 748         .p0_mprddlctl =    0x44444846,
 749         .p1_mprddlctl =    0x4042463C,
 750         .p0_mpwrdlctl =    0x32343032,
 751         .p1_mpwrdlctl =    0x36363430,
 752 };
 753
 754 static struct mx6_ddr3_cfg mem_ddr_2g = {
 755         .mem_speed = 1600,
 756         .density   = 2,
 757         .width     = 16,
 758         .banks     = 8,
 759         .rowaddr   = 14,
 760         .coladdr   = 10,
 761         .pagesz    = 2,
 762         .trcd      = 1375,
 763         .trcmin    = 4875,
 764         .trasmin   = 3500,
 765 };
 766
 767 static struct mx6_ddr3_cfg mem_ddr_4g = {
 768         .mem_speed = 1600,
 769         .density = 4,
 770         .width = 16,
 771         .banks = 8,
 772         .rowaddr = 16,
 773         .coladdr = 10,
 774         .pagesz = 2,
 775         .trcd = 1375,
 776         .trcmin = 4875,
 777         .trasmin = 3500,
 778 };
 779
 780 static void ccgr_init(void)
 781 {
 782         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 783
 784         writel(0x00C03F3F, &ccm->CCGR0);
 785         writel(0x0030FC03, &ccm->CCGR1);
 786         writel(0x0FFFC000, &ccm->CCGR2);
 787         writel(0x3FF00000, &ccm->CCGR3);
 788         writel(0x00FFF300, &ccm->CCGR4);
 789         writel(0x0F0000C3, &ccm->CCGR5);
 790         writel(0x000003FF, &ccm->CCGR6);
 791 }
 792
 793 static void spl_dram_init(int width)
 794 {
 795         struct mx6_ddr_sysinfo sysinfo = {
 796                 /* width of data bus: 0=16, 1=32, 2=64 */
 797                 .dsize = width / 32,
 798                 /* config for full 4GB range so that get_mem_size() works */
 799                 .cs_density = 32,       /* 32Gb per CS */
 800                 .ncs = 1,               /* single chip select */
 801                 .cs1_mirror = 0,
 802                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 803                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 804                 .walat = 1,     /* Write additional latency */
 805                 .ralat = 5,     /* Read additional latency */
 806                 .mif3_mode = 3, /* Command prediction working mode */
 807                 .bi_on = 1,     /* Bank interleaving enabled */
 808                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 809                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 810                 .ddr_type = DDR_TYPE_DDR3,
 811                 .refsel = 1,    /* Refresh cycles at 32KHz */
 812                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 813         };
 814
 815         if (is_mx6dq())
 816                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 817         else
 818                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 819
 820         if (is_cpu_type(MXC_CPU_MX6D))
 821                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 822         else if (is_cpu_type(MXC_CPU_MX6Q))
 823                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 824         else if (is_cpu_type(MXC_CPU_MX6DL))
 825                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 826         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 827                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 828 }
 829
 830 void board_init_f(ulong dummy)
 831 {
 832         /* setup AIPS and disable watchdog */
 833         arch_cpu_init();
 834
 835         ccgr_init();
 836         gpr_init();
 837
 838         /* iomux and setup of i2c */
 839         board_early_init_f();
 840
 841         /* setup GP timer */
 842         timer_init();
 843
 844         /* UART clocks enabled and gd valid - init serial console */
 845         preloader_console_init();
 846
 847         /* DDR initialization */
 848         if (is_cpu_type(MXC_CPU_MX6SOLO))
 849                 spl_dram_init(32);
 850         else
 851                 spl_dram_init(64);
 852
 853         /* Clear the BSS. */
 854         memset(__bss_start, 0, __bss_end - __bss_start);
 855
 856         /* load/boot image from boot device */
 857         board_init_r(NULL, 0);
 858 }
 859 #endif