board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   8  *
   9  * Based on SPL code from Solidrun tree, which is:
  10  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11  *
  12  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14  */
  15
  16 #include <common.h>
  17 #include <init.h>
  18 #include <net.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <env.h>
  25 #include <linux/errno.h>
  26 #include <asm/gpio.h>
  27 #include <asm/mach-imx/iomux-v3.h>
  28 #include <asm/mach-imx/sata.h>
  29 #include <asm/mach-imx/video.h>
  30 #include <mmc.h>
  31 #include <fsl_esdhc_imx.h>
  32 #include <malloc.h>
  33 #include <miiphy.h>
  34 #include <netdev.h>
  35 #include <asm/arch/crm_regs.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/sys_proto.h>
  38 #include <spl.h>
  39 #include <usb.h>
  40 #include <usb/ehci-ci.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  60
  61 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  62 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  63
  64 enum board_type {
  65         CUBOXI          = 0x00,
  66         HUMMINGBOARD    = 0x01,
  67         HUMMINGBOARD2   = 0x02,
  68         UNKNOWN         = 0x03,
  69 };
  70
  71 static struct gpio_desc board_detect_desc[5];
  72
  73 #define MEM_STRIDE 0x4000000
  74 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  75 {
  76         volatile u32 *addr;
  77         u32          save[64];
  78         u32          cnt;
  79         u32          size;
  80         int          i = 0;
  81
  82         /* First save the data */
  83         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  84                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  85                 sync ();
  86                 save[i++] = *addr;
  87                 sync ();
  88         }
  89
  90         /* First write a signature */
  91         * (volatile u32 *)base = 0x12345678;
  92         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  93                 * (volatile u32 *)((u32)base + size) = size;
  94                 sync ();
  95                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  96                         break;
  97                 }
  98         }
  99
 100         /* Restore the data */
 101         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
 102                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
 103                 sync ();
 104                 *addr = save[i--];
 105                 sync ();
 106         }
 107
 108         return (size);
 109 }
 110
 111 int dram_init(void)
 112 {
 113         u32 max_size = imx_ddr_size();
 114
 115         gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
 116                                                 (u32)max_size);
 117
 118         return 0;
 119 }
 120
 121 static iomux_v3_cfg_t const uart1_pads[] = {
 122         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 123         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 124 };
 125
 126 static iomux_v3_cfg_t const usdhc2_pads[] = {
 127         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133 };
 134
 135 static iomux_v3_cfg_t const usdhc3_pads[] = {
 136         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 145         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 146         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 147 };
 148
 149 static iomux_v3_cfg_t const board_detect[] = {
 150         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 151         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 152         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 153         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 154 };
 155
 156 static iomux_v3_cfg_t const som_rev_detect[] = {
 157         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 158         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 159         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 160 };
 161
 162 static void setup_iomux_uart(void)
 163 {
 164         SETUP_IOMUX_PADS(uart1_pads);
 165 }
 166
 167 static struct fsl_esdhc_cfg usdhc_cfg = {
 168         .esdhc_base = USDHC2_BASE_ADDR,
 169         .max_bus_width = 4,
 170 };
 171
 172 static struct fsl_esdhc_cfg emmc_cfg = {
 173         .esdhc_base = USDHC3_BASE_ADDR,
 174         .max_bus_width = 8,
 175 };
 176
 177 int board_mmc_get_env_dev(int devno)
 178 {
 179         return devno;
 180 }
 181
 182 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 183
 184 int board_mmc_getcd(struct mmc *mmc)
 185 {
 186         struct fsl_esdhc_cfg *cfg = mmc->priv;
 187         int ret = 0;
 188
 189         switch (cfg->esdhc_base) {
 190         case USDHC2_BASE_ADDR:
 191                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 192                 break;
 193         case USDHC3_BASE_ADDR:
 194                 ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
 195                 break;
 196         }
 197
 198         return ret;
 199 }
 200
 201 static int mmc_init_spl(bd_t *bis)
 202 {
 203         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 204         unsigned reg = readl(&psrc->sbmr1) >> 11;
 205
 206         /*
 207          * Upon reading BOOT_CFG register the following map is done:
 208          * Bit 11 and 12 of BOOT_CFG register can determine the current
 209          * mmc port
 210          * 0x1                  SD2
 211          * 0x2                  SD3
 212          */
 213         switch (reg & 0x3) {
 214         case 0x1:
 215                 SETUP_IOMUX_PADS(usdhc2_pads);
 216                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 217                 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 218                 return fsl_esdhc_initialize(bis, &usdhc_cfg);
 219         case 0x2:
 220                 SETUP_IOMUX_PADS(usdhc3_pads);
 221                 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 222                 gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
 223                 return fsl_esdhc_initialize(bis, &emmc_cfg);
 224         }
 225
 226         return -ENODEV;
 227 }
 228
 229 int board_mmc_init(bd_t *bis)
 230 {
 231         if (IS_ENABLED(CONFIG_SPL_BUILD))
 232                 return mmc_init_spl(bis);
 233
 234         return 0;
 235 }
 236
 237 static iomux_v3_cfg_t const enet_pads[] = {
 238         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 239         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 240         /* AR8035 reset */
 241         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 242         /* AR8035 interrupt */
 243         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 244         /* GPIO16 -> AR8035 25MHz */
 245         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 246         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 247         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 248         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 249         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 250         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 251         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 252         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 253         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 254         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 255         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 256         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 257         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 258         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 259         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 260         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 261         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 262 };
 263
 264 static void setup_iomux_enet(void)
 265 {
 266         struct gpio_desc desc;
 267         int ret;
 268
 269         SETUP_IOMUX_PADS(enet_pads);
 270
 271         ret = dm_gpio_lookup_name("GPIO4_15", &desc);
 272         if (ret) {
 273                 printf("%s: phy reset lookup failed\n", __func__);
 274                 return;
 275         }
 276
 277         ret = dm_gpio_request(&desc, "phy-reset");
 278         if (ret) {
 279                 printf("%s: phy reset request failed\n", __func__);
 280                 return;
 281         }
 282
 283         gpio_direction_output(ETH_PHY_RESET, 0);
 284         mdelay(10);
 285         gpio_set_value(ETH_PHY_RESET, 1);
 286         udelay(100);
 287
 288         gpio_free_list_nodev(&desc, 1);
 289 }
 290
 291 int board_phy_config(struct phy_device *phydev)
 292 {
 293         if (phydev->drv->config)
 294                 phydev->drv->config(phydev);
 295
 296         return 0;
 297 }
 298
 299 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 300 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 301
 302 int board_eth_init(bd_t *bis)
 303 {
 304         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 305         struct mii_dev *bus;
 306         struct phy_device *phydev;
 307
 308         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 309         if (ret)
 310                 return ret;
 311
 312         /* set gpr1[ENET_CLK_SEL] */
 313         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 314
 315         setup_iomux_enet();
 316
 317         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 318         if (!bus)
 319                 return -EINVAL;
 320
 321         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 322         if (!phydev) {
 323                 ret = -EINVAL;
 324                 goto free_bus;
 325         }
 326
 327         debug("using phy at address %d\n", phydev->addr);
 328         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 329         if (ret)
 330                 goto free_phydev;
 331
 332         return 0;
 333
 334 free_phydev:
 335         free(phydev);
 336 free_bus:
 337         free(bus);
 338         return ret;
 339 }
 340
 341 #ifdef CONFIG_VIDEO_IPUV3
 342 static void do_enable_hdmi(struct display_info_t const *dev)
 343 {
 344         imx_enable_hdmi_phy();
 345 }
 346
 347 struct display_info_t const displays[] = {
 348         {
 349                 .bus    = -1,
 350                 .addr   = 0,
 351                 .pixfmt = IPU_PIX_FMT_RGB24,
 352                 .detect = detect_hdmi,
 353                 .enable = do_enable_hdmi,
 354                 .mode   = {
 355                         .name           = "HDMI",
 356                         /* 1024x768@60Hz (VESA)*/
 357                         .refresh        = 60,
 358                         .xres           = 1024,
 359                         .yres           = 768,
 360                         .pixclock       = 15384,
 361                         .left_margin    = 160,
 362                         .right_margin   = 24,
 363                         .upper_margin   = 29,
 364                         .lower_margin   = 3,
 365                         .hsync_len      = 136,
 366                         .vsync_len      = 6,
 367                         .sync           = FB_SYNC_EXT,
 368                         .vmode          = FB_VMODE_NONINTERLACED
 369                 }
 370         }
 371 };
 372
 373 size_t display_count = ARRAY_SIZE(displays);
 374
 375 static int setup_display(void)
 376 {
 377         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 378         int reg;
 379         int timeout = 100000;
 380
 381         enable_ipu_clock();
 382         imx_setup_hdmi();
 383
 384         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 385         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 386
 387         reg = readl(&ccm->analog_pll_video);
 388         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 389         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 390         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 391         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 392         writel(reg, &ccm->analog_pll_video);
 393
 394         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 395         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 396
 397         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 398         writel(reg, &ccm->analog_pll_video);
 399
 400         while (timeout--)
 401                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 402                         break;
 403         if (timeout < 0) {
 404                 printf("Warning: video pll lock timeout!\n");
 405                 return -ETIMEDOUT;
 406         }
 407
 408         reg = readl(&ccm->analog_pll_video);
 409         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 410         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 411         writel(reg, &ccm->analog_pll_video);
 412
 413         /* gate ipu1_di0_clk */
 414         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 415
 416         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 417         reg = readl(&ccm->chsccdr);
 418         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 419                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 420                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 421         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 422                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 423                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 424         writel(reg, &ccm->chsccdr);
 425
 426         /* enable ipu1_di0_clk */
 427         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 428
 429         return 0;
 430 }
 431 #endif /* CONFIG_VIDEO_IPUV3 */
 432
 433 int board_early_init_f(void)
 434 {
 435         setup_iomux_uart();
 436
 437 #ifdef CONFIG_CMD_SATA
 438         setup_sata();
 439 #endif
 440         return 0;
 441 }
 442
 443 int board_init(void)
 444 {
 445         int ret = 0;
 446
 447         /* address of boot parameters */
 448         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 449
 450 #ifdef CONFIG_VIDEO_IPUV3
 451         ret = setup_display();
 452 #endif
 453
 454         return ret;
 455 }
 456
 457 static int request_detect_gpios(void)
 458 {
 459         int node;
 460         int ret;
 461
 462         node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
 463                 "solidrun,hummingboard-detect");
 464         if (node < 0)
 465                 return -ENODEV;
 466
 467         ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
 468                 "detect-gpios", board_detect_desc,
 469                 ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
 470
 471         return ret;
 472 }
 473
 474 static int free_detect_gpios(void)
 475 {
 476         return gpio_free_list_nodev(board_detect_desc,
 477                 ARRAY_SIZE(board_detect_desc));
 478 }
 479
 480 static enum board_type board_type(void)
 481 {
 482         int val1, val2, val3;
 483
 484         SETUP_IOMUX_PADS(board_detect);
 485
 486         /*
 487          * Machine selection -
 488          * Machine      val1, val2, val3
 489          * ----------------------------
 490          * HB2            x     x    0
 491          * HB rev 3.x     x     0    x
 492          * CBi            0     1    x
 493          * HB             1     1    x
 494          */
 495
 496         gpio_direction_input(IMX_GPIO_NR(2, 8));
 497         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 498
 499         if (val3 == 0)
 500                 return HUMMINGBOARD2;
 501
 502         gpio_direction_input(IMX_GPIO_NR(3, 4));
 503         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 504
 505         if (val2 == 0)
 506                 return HUMMINGBOARD;
 507
 508         gpio_direction_input(IMX_GPIO_NR(4, 9));
 509         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 510
 511         if (val1 == 0) {
 512                 return CUBOXI;
 513         } else {
 514                 return HUMMINGBOARD;
 515         }
 516 }
 517
 518 static bool is_rev_15_som(void)
 519 {
 520         int val1, val2;
 521         SETUP_IOMUX_PADS(som_rev_detect);
 522
 523         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 524         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 525
 526         if (val1 == 1 && val2 == 0)
 527                 return true;
 528
 529         return false;
 530 }
 531
 532 static bool has_emmc(void)
 533 {
 534         struct mmc *mmc;
 535         mmc = find_mmc_device(2);
 536         if (!mmc)
 537                 return 0;
 538         return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
 539 }
 540
 541 int checkboard(void)
 542 {
 543         request_detect_gpios();
 544
 545         switch (board_type()) {
 546         case CUBOXI:
 547                 puts("Board: MX6 Cubox-i");
 548                 break;
 549         case HUMMINGBOARD:
 550                 puts("Board: MX6 HummingBoard");
 551                 break;
 552         case HUMMINGBOARD2:
 553                 puts("Board: MX6 HummingBoard2");
 554                 break;
 555         case UNKNOWN:
 556         default:
 557                 puts("Board: Unknown\n");
 558                 goto out;
 559         }
 560
 561         if (is_rev_15_som())
 562                 puts(" (som rev 1.5)\n");
 563         else
 564                 puts("\n");
 565
 566         free_detect_gpios();
 567 out:
 568         return 0;
 569 }
 570
 571 /* Override the default implementation, DT model is not accurate */
 572 int show_board_info(void)
 573 {
 574         return checkboard();
 575 }
 576
 577 int board_late_init(void)
 578 {
 579 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 580         request_detect_gpios();
 581
 582         switch (board_type()) {
 583         case CUBOXI:
 584                 env_set("board_name", "CUBOXI");
 585                 break;
 586         case HUMMINGBOARD:
 587                 env_set("board_name", "HUMMINGBOARD");
 588                 break;
 589         case HUMMINGBOARD2:
 590                 env_set("board_name", "HUMMINGBOARD2");
 591                 break;
 592         case UNKNOWN:
 593         default:
 594                 env_set("board_name", "CUBOXI");
 595         }
 596
 597         if (is_mx6dq())
 598                 env_set("board_rev", "MX6Q");
 599         else
 600                 env_set("board_rev", "MX6DL");
 601
 602         if (is_rev_15_som())
 603                 env_set("som_rev", "V15");
 604
 605         if (has_emmc())
 606                 env_set("has_emmc", "yes");
 607
 608         free_detect_gpios();
 609 #endif
 610
 611         return 0;
 612 }
 613
 614 /*
 615  * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
 616  * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
 617  * all Hummingboard/Cubox-i platforms.
 618  */
 619 int board_fit_config_name_match(const char *name)
 620 {
 621         char tmp_name[36];
 622
 623         snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
 624                         is_mx6dq() ? "imx6q" : "imx6dl");
 625
 626         return strcmp(name, tmp_name);
 627 }
 628
 629 #ifdef CONFIG_SPL_BUILD
 630 #include <asm/arch/mx6-ddr.h>
 631 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 632         .dram_sdclk_0 =  0x00020030,
 633         .dram_sdclk_1 =  0x00020030,
 634         .dram_cas =  0x00020030,
 635         .dram_ras =  0x00020030,
 636         .dram_reset =  0x000c0030,
 637         .dram_sdcke0 =  0x00003000,
 638         .dram_sdcke1 =  0x00003000,
 639         .dram_sdba2 =  0x00000000,
 640         .dram_sdodt0 =  0x00003030,
 641         .dram_sdodt1 =  0x00003030,
 642         .dram_sdqs0 =  0x00000030,
 643         .dram_sdqs1 =  0x00000030,
 644         .dram_sdqs2 =  0x00000030,
 645         .dram_sdqs3 =  0x00000030,
 646         .dram_sdqs4 =  0x00000030,
 647         .dram_sdqs5 =  0x00000030,
 648         .dram_sdqs6 =  0x00000030,
 649         .dram_sdqs7 =  0x00000030,
 650         .dram_dqm0 =  0x00020030,
 651         .dram_dqm1 =  0x00020030,
 652         .dram_dqm2 =  0x00020030,
 653         .dram_dqm3 =  0x00020030,
 654         .dram_dqm4 =  0x00020030,
 655         .dram_dqm5 =  0x00020030,
 656         .dram_dqm6 =  0x00020030,
 657         .dram_dqm7 =  0x00020030,
 658 };
 659
 660 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 661         .dram_sdclk_0 = 0x00000028,
 662         .dram_sdclk_1 = 0x00000028,
 663         .dram_cas =     0x00000028,
 664         .dram_ras =     0x00000028,
 665         .dram_reset =   0x000c0028,
 666         .dram_sdcke0 =  0x00003000,
 667         .dram_sdcke1 =  0x00003000,
 668         .dram_sdba2 =   0x00000000,
 669         .dram_sdodt0 =  0x00003030,
 670         .dram_sdodt1 =  0x00003030,
 671         .dram_sdqs0 =   0x00000028,
 672         .dram_sdqs1 =   0x00000028,
 673         .dram_sdqs2 =   0x00000028,
 674         .dram_sdqs3 =   0x00000028,
 675         .dram_sdqs4 =   0x00000028,
 676         .dram_sdqs5 =   0x00000028,
 677         .dram_sdqs6 =   0x00000028,
 678         .dram_sdqs7 =   0x00000028,
 679         .dram_dqm0 =    0x00000028,
 680         .dram_dqm1 =    0x00000028,
 681         .dram_dqm2 =    0x00000028,
 682         .dram_dqm3 =    0x00000028,
 683         .dram_dqm4 =    0x00000028,
 684         .dram_dqm5 =    0x00000028,
 685         .dram_dqm6 =    0x00000028,
 686         .dram_dqm7 =    0x00000028,
 687 };
 688
 689 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 690         .grp_ddr_type =  0x000C0000,
 691         .grp_ddrmode_ctl =  0x00020000,
 692         .grp_ddrpke =  0x00000000,
 693         .grp_addds =  0x00000030,
 694         .grp_ctlds =  0x00000030,
 695         .grp_ddrmode =  0x00020000,
 696         .grp_b0ds =  0x00000030,
 697         .grp_b1ds =  0x00000030,
 698         .grp_b2ds =  0x00000030,
 699         .grp_b3ds =  0x00000030,
 700         .grp_b4ds =  0x00000030,
 701         .grp_b5ds =  0x00000030,
 702         .grp_b6ds =  0x00000030,
 703         .grp_b7ds =  0x00000030,
 704 };
 705
 706 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 707         .grp_ddr_type = 0x000c0000,
 708         .grp_ddrmode_ctl = 0x00020000,
 709         .grp_ddrpke = 0x00000000,
 710         .grp_addds = 0x00000028,
 711         .grp_ctlds = 0x00000028,
 712         .grp_ddrmode = 0x00020000,
 713         .grp_b0ds = 0x00000028,
 714         .grp_b1ds = 0x00000028,
 715         .grp_b2ds = 0x00000028,
 716         .grp_b3ds = 0x00000028,
 717         .grp_b4ds = 0x00000028,
 718         .grp_b5ds = 0x00000028,
 719         .grp_b6ds = 0x00000028,
 720         .grp_b7ds = 0x00000028,
 721 };
 722
 723 /* microSOM with Dual processor and 1GB memory */
 724 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 725         .p0_mpwldectrl0 =  0x00000000,
 726         .p0_mpwldectrl1 =  0x00000000,
 727         .p1_mpwldectrl0 =  0x00000000,
 728         .p1_mpwldectrl1 =  0x00000000,
 729         .p0_mpdgctrl0 =    0x0314031c,
 730         .p0_mpdgctrl1 =    0x023e0304,
 731         .p1_mpdgctrl0 =    0x03240330,
 732         .p1_mpdgctrl1 =    0x03180260,
 733         .p0_mprddlctl =    0x3630323c,
 734         .p1_mprddlctl =    0x3436283a,
 735         .p0_mpwrdlctl =    0x36344038,
 736         .p1_mpwrdlctl =    0x422a423c,
 737 };
 738
 739 /* microSOM with Quad processor and 2GB memory */
 740 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 741         .p0_mpwldectrl0 =  0x00000000,
 742         .p0_mpwldectrl1 =  0x00000000,
 743         .p1_mpwldectrl0 =  0x00000000,
 744         .p1_mpwldectrl1 =  0x00000000,
 745         .p0_mpdgctrl0 =    0x0314031c,
 746         .p0_mpdgctrl1 =    0x023e0304,
 747         .p1_mpdgctrl0 =    0x03240330,
 748         .p1_mpdgctrl1 =    0x03180260,
 749         .p0_mprddlctl =    0x3630323c,
 750         .p1_mprddlctl =    0x3436283a,
 751         .p0_mpwrdlctl =    0x36344038,
 752         .p1_mpwrdlctl =    0x422a423c,
 753 };
 754
 755 /* microSOM with Solo processor and 512MB memory */
 756 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 757         .p0_mpwldectrl0 = 0x0045004D,
 758         .p0_mpwldectrl1 = 0x003A0047,
 759         .p0_mpdgctrl0 =   0x023C0224,
 760         .p0_mpdgctrl1 =   0x02000220,
 761         .p0_mprddlctl =   0x44444846,
 762         .p0_mpwrdlctl =   0x32343032,
 763 };
 764
 765 /* microSOM with Dual lite processor and 1GB memory */
 766 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 767         .p0_mpwldectrl0 =  0x0045004D,
 768         .p0_mpwldectrl1 =  0x003A0047,
 769         .p1_mpwldectrl0 =  0x001F001F,
 770         .p1_mpwldectrl1 =  0x00210035,
 771         .p0_mpdgctrl0 =    0x023C0224,
 772         .p0_mpdgctrl1 =    0x02000220,
 773         .p1_mpdgctrl0 =    0x02200220,
 774         .p1_mpdgctrl1 =    0x02040208,
 775         .p0_mprddlctl =    0x44444846,
 776         .p1_mprddlctl =    0x4042463C,
 777         .p0_mpwrdlctl =    0x32343032,
 778         .p1_mpwrdlctl =    0x36363430,
 779 };
 780
 781 static struct mx6_ddr3_cfg mem_ddr_2g = {
 782         .mem_speed = 1600,
 783         .density   = 2,
 784         .width     = 16,
 785         .banks     = 8,
 786         .rowaddr   = 14,
 787         .coladdr   = 10,
 788         .pagesz    = 2,
 789         .trcd      = 1375,
 790         .trcmin    = 4875,
 791         .trasmin   = 3500,
 792 };
 793
 794 static struct mx6_ddr3_cfg mem_ddr_4g = {
 795         .mem_speed = 1600,
 796         .density = 4,
 797         .width = 16,
 798         .banks = 8,
 799         .rowaddr = 16,
 800         .coladdr = 10,
 801         .pagesz = 2,
 802         .trcd = 1375,
 803         .trcmin = 4875,
 804         .trasmin = 3500,
 805 };
 806
 807 static void ccgr_init(void)
 808 {
 809         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 810
 811         writel(0x00C03F3F, &ccm->CCGR0);
 812         writel(0x0030FC03, &ccm->CCGR1);
 813         writel(0x0FFFC000, &ccm->CCGR2);
 814         writel(0x3FF00000, &ccm->CCGR3);
 815         writel(0x00FFF300, &ccm->CCGR4);
 816         writel(0x0F0000C3, &ccm->CCGR5);
 817         writel(0x000003FF, &ccm->CCGR6);
 818 }
 819
 820 static void spl_dram_init(int width)
 821 {
 822         struct mx6_ddr_sysinfo sysinfo = {
 823                 /* width of data bus: 0=16, 1=32, 2=64 */
 824                 .dsize = width / 32,
 825                 /* config for full 4GB range so that get_mem_size() works */
 826                 .cs_density = 32,       /* 32Gb per CS */
 827                 .ncs = 1,               /* single chip select */
 828                 .cs1_mirror = 0,
 829                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 830                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 831                 .walat = 1,     /* Write additional latency */
 832                 .ralat = 5,     /* Read additional latency */
 833                 .mif3_mode = 3, /* Command prediction working mode */
 834                 .bi_on = 1,     /* Bank interleaving enabled */
 835                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 836                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 837                 .ddr_type = DDR_TYPE_DDR3,
 838                 .refsel = 1,    /* Refresh cycles at 32KHz */
 839                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 840         };
 841
 842         if (is_mx6dq())
 843                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 844         else
 845                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 846
 847         if (is_cpu_type(MXC_CPU_MX6D))
 848                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 849         else if (is_cpu_type(MXC_CPU_MX6Q))
 850                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 851         else if (is_cpu_type(MXC_CPU_MX6DL))
 852                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 853         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 854                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 855 }
 856
 857 void board_init_f(ulong dummy)
 858 {
 859         /* setup AIPS and disable watchdog */
 860         arch_cpu_init();
 861
 862         ccgr_init();
 863         gpr_init();
 864
 865         /* iomux and setup of i2c */
 866         board_early_init_f();
 867
 868         /* setup GP timer */
 869         timer_init();
 870
 871         /* UART clocks enabled and gd valid - init serial console */
 872         preloader_console_init();
 873
 874         /* DDR initialization */
 875         if (is_cpu_type(MXC_CPU_MX6SOLO))
 876                 spl_dram_init(32);
 877         else
 878                 spl_dram_init(64);
 879
 880         /* Clear the BSS. */
 881         memset(__bss_start, 0, __bss_end - __bss_start);
 882
 883         /* load/boot image from boot device */
 884         board_init_r(NULL, 0);
 885 }
 886 #endif