2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013 SolidRun ltd.
4 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
6 * Authors: Fabio Estevam <fabio.estevam@freescale.com>
7 Jon Nettleton <jon.nettleton@gmail.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/errno.h>
20 #include <asm/imx-common/iomux-v3.h>
23 #include <fsl_esdhc.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
41 #define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
54 #define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
58 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
63 static iomux_v3_cfg_t const uart1_pads[] = {
64 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
68 static void setup_iomux_uart(void)
70 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
73 static iomux_v3_cfg_t const usdhc2_pads[] = {
74 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
75 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
83 #ifdef CONFIG_FSL_ESDHC
84 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
88 int board_mmc_getcd(struct mmc *mmc)
90 return 1; /* SD card is the boot medium, so always present */
93 int board_mmc_init(bd_t *bis)
95 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
96 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
98 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
102 #ifdef CONFIG_FEC_MXC
103 static iomux_v3_cfg_t const enet_pads[] = {
104 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
108 /* AR8035 interrupt */
109 MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 /* GPIO16 -> AR8035 25MHz */
111 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
112 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
119 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
120 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
122 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
123 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
128 static void setup_iomux_enet(void)
130 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
132 gpio_direction_output(ETH_PHY_RESET, 0);
134 gpio_set_value(ETH_PHY_RESET, 1);
137 int board_phy_config(struct phy_device *phydev)
139 if (phydev->drv->config)
140 phydev->drv->config(phydev);
145 int board_eth_init(bd_t *bis)
147 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
149 int ret = enable_fec_anatop_clock(ENET_25MHZ);
153 /* set gpr1[ENET_CLK_SEL] */
154 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
158 return cpu_eth_init(bis);
162 int board_early_init_f(void)
171 /* address of boot parameters */
172 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
179 puts("Board: Hummingboard\n");