1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include "../common/tlv_data.h"
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Those values and defines are taken from the Marvell U-Boot version
22 * "u-boot-2013.01-15t1-clearfog"
24 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
25 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
27 #define BOARD_GPP_OUT_VAL_LOW 0x0
28 #define BOARD_GPP_OUT_VAL_MID 0x0
29 #define BOARD_GPP_POL_LOW 0x0
30 #define BOARD_GPP_POL_MID 0x0
32 static struct tlv_data cf_tlv_data;
34 static void cf_read_tlv_data(void)
36 static bool read_once;
42 read_tlv_data(&cf_tlv_data);
45 static struct serdes_map board_serdes_map[] = {
46 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
47 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
48 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
49 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
50 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
51 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
58 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
59 board_serdes_map[0].serdes_type = PEX0;
60 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
61 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
64 if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
65 board_serdes_map[4].serdes_type = USB3_HOST0;
66 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
67 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
70 *serdes_map_array = board_serdes_map;
71 *count = ARRAY_SIZE(board_serdes_map);
76 * Define the DDR layout / topology here in the board file. This will
77 * be used by the DDR3 init code in the SPL U-Boot version to configure
78 * the DDR3 controller.
80 static struct mv_ddr_topology_map board_topology_map = {
82 0x1, /* active interfaces */
83 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
89 SPEED_BIN_DDR_1600K, /* speed_bin */
90 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
91 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
92 MV_DDR_FREQ_800, /* frequency */
93 0, 0, /* cas_wl cas_l */
94 MV_DDR_TEMP_LOW, /* temperature */
95 MV_DDR_TIM_DEFAULT} }, /* timing */
96 BUS_MASK_32BIT, /* Busses mask */
97 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
98 { {0} }, /* raw spd data */
99 {0}, /* timing parameters */
100 { {0} }, /* electrical configuration */
101 {0,}, /* electrical parameters */
102 0x3, /* clock enable mask */
105 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
107 struct if_params *ifp = &board_topology_map.interface_params[0];
111 switch (cf_tlv_data.ram_size) {
114 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
117 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
121 /* Return the board topology as defined in the board code */
122 return &board_topology_map;
125 int board_early_init_f(void)
128 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
129 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
130 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
131 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
132 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
133 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
134 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
135 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
137 /* Set GPP Out value */
138 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
139 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
141 /* Set GPP Polarity */
142 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
143 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
145 /* Set GPP Out Enable */
146 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
147 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
154 /* Address of boot parameters */
155 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
157 /* Toggle GPIO41 to reset onboard switch and phy */
158 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
159 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
160 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
161 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
162 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
164 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
165 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
173 char *board = "ClearFog";
176 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
177 board = cf_tlv_data.tlv_product_name[0];
179 printf("Board: SolidRun %s", board);
180 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
181 printf(", %s", cf_tlv_data.tlv_product_name[1]);
187 int board_eth_init(bd_t *bis)
189 cpu_eth_init(bis); /* Built in controller(s) come first */
190 return pci_eth_init(bis);
193 int board_late_init(void)
197 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
198 env_set("fdtfile", "armada-388-clearfog-base.dtb");
199 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
200 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
201 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
202 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");