1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
15 #include <../serdes/a38x/high_speed_env_spec.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define ETH_PHY_CTRL_REG 0
20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2013.01-15t1-clearfog"
27 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
28 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
30 #define BOARD_GPP_OUT_VAL_LOW 0x0
31 #define BOARD_GPP_OUT_VAL_MID 0x0
32 #define BOARD_GPP_POL_LOW 0x0
33 #define BOARD_GPP_POL_MID 0x0
35 static struct serdes_map board_serdes_map[] = {
36 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
37 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
38 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
39 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
40 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
41 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
44 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
46 *serdes_map_array = board_serdes_map;
47 *count = ARRAY_SIZE(board_serdes_map);
52 * Define the DDR layout / topology here in the board file. This will
53 * be used by the DDR3 init code in the SPL U-Boot version to configure
54 * the DDR3 controller.
56 static struct mv_ddr_topology_map board_topology_map = {
58 0x1, /* active interfaces */
59 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
65 SPEED_BIN_DDR_1600K, /* speed_bin */
66 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
67 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
68 MV_DDR_FREQ_800, /* frequency */
69 0, 0, /* cas_wl cas_l */
70 MV_DDR_TEMP_LOW, /* temperature */
71 MV_DDR_TIM_DEFAULT} }, /* timing */
72 BUS_MASK_32BIT, /* Busses mask */
73 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
74 { {0} }, /* raw spd data */
75 {0} /* timing parameters */
78 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
80 /* Return the board topology as defined in the board code */
81 return &board_topology_map;
84 int board_early_init_f(void)
87 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
88 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
89 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
90 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
91 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
92 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
93 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
94 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
96 /* Set GPP Out value */
97 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
98 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
100 /* Set GPP Polarity */
101 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
102 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
104 /* Set GPP Out Enable */
105 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
106 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
113 /* Address of boot parameters */
114 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
116 /* Toggle GPIO41 to reset onboard switch and phy */
117 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
118 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
119 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
120 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
121 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
123 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
124 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
132 puts("Board: SolidRun ClearFog\n");
137 int board_eth_init(bd_t *bis)
139 cpu_eth_init(bis); /* Built in controller(s) come first */
140 return pci_eth_init(bis);