1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include "../common/tlv_data.h"
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Those values and defines are taken from the Marvell U-Boot version
22 * "u-boot-2013.01-15t1-clearfog"
24 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
25 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
27 #define BOARD_GPP_OUT_VAL_LOW 0x0
28 #define BOARD_GPP_OUT_VAL_MID 0x0
29 #define BOARD_GPP_POL_LOW 0x0
30 #define BOARD_GPP_POL_MID 0x0
32 static struct tlv_data cf_tlv_data;
34 static void cf_read_tlv_data(void)
36 static bool read_once;
42 read_tlv_data(&cf_tlv_data);
45 static struct serdes_map board_serdes_map[] = {
46 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
47 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
48 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
49 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
50 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
51 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
56 *serdes_map_array = board_serdes_map;
57 *count = ARRAY_SIZE(board_serdes_map);
62 * Define the DDR layout / topology here in the board file. This will
63 * be used by the DDR3 init code in the SPL U-Boot version to configure
64 * the DDR3 controller.
66 static struct mv_ddr_topology_map board_topology_map = {
68 0x1, /* active interfaces */
69 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
75 SPEED_BIN_DDR_1600K, /* speed_bin */
76 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
77 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
78 MV_DDR_FREQ_800, /* frequency */
79 0, 0, /* cas_wl cas_l */
80 MV_DDR_TEMP_LOW, /* temperature */
81 MV_DDR_TIM_DEFAULT} }, /* timing */
82 BUS_MASK_32BIT, /* Busses mask */
83 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
84 { {0} }, /* raw spd data */
85 {0}, /* timing parameters */
86 { {0} }, /* electrical configuration */
87 {0,}, /* electrical parameters */
88 0x3, /* clock enable mask */
91 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
93 struct if_params *ifp = &board_topology_map.interface_params[0];
97 switch (cf_tlv_data.ram_size) {
100 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
103 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
107 /* Return the board topology as defined in the board code */
108 return &board_topology_map;
111 int board_early_init_f(void)
114 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
115 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
116 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
117 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
118 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
119 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
120 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
121 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
123 /* Set GPP Out value */
124 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
125 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
127 /* Set GPP Polarity */
128 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
129 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
131 /* Set GPP Out Enable */
132 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
133 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
140 /* Address of boot parameters */
141 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
143 /* Toggle GPIO41 to reset onboard switch and phy */
144 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
145 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
146 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
147 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
148 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
150 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
151 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
159 char *board = "ClearFog";
162 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
163 board = cf_tlv_data.tlv_product_name[0];
165 printf("Board: SolidRun %s", board);
166 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
167 printf(", %s", cf_tlv_data.tlv_product_name[1]);
173 int board_eth_init(bd_t *bis)
175 cpu_eth_init(bis); /* Built in controller(s) come first */
176 return pci_eth_init(bis);