1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include "../common/tlv_data.h"
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Those values and defines are taken from the Marvell U-Boot version
22 * "u-boot-2013.01-15t1-clearfog"
24 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
25 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
27 #define BOARD_GPP_OUT_VAL_LOW 0x0
28 #define BOARD_GPP_OUT_VAL_MID 0x0
29 #define BOARD_GPP_POL_LOW 0x0
30 #define BOARD_GPP_POL_MID 0x0
32 static struct tlv_data cf_tlv_data;
34 static void cf_read_tlv_data(void)
36 static bool read_once;
42 read_tlv_data(&cf_tlv_data);
45 /* The starting board_serdes_map reflects original Clearfog Pro usage */
46 static struct serdes_map board_serdes_map[] = {
47 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
48 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
49 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
50 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
51 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
52 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
55 void config_cfbase_serdes_map(void)
57 board_serdes_map[4].serdes_type = USB3_HOST0;
58 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
59 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
62 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
66 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
67 board_serdes_map[0].serdes_type = PEX0;
68 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
69 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
70 } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
71 /* handle recognized product as noop, no adjustment required */
72 } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
73 config_cfbase_serdes_map();
76 * Fallback to static default. EEPROM TLV support is not
77 * enabled, runtime detection failed, hardware support is not
78 * present, EEPROM is corrupt, or an unrecognized product name
81 if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
82 puts("EEPROM TLV detection failed: ");
83 puts("Using static config for ");
84 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
85 puts("Clearfog Base.\n");
86 config_cfbase_serdes_map();
88 puts("Clearfog Pro.\n");
92 *serdes_map_array = board_serdes_map;
93 *count = ARRAY_SIZE(board_serdes_map);
98 * Define the DDR layout / topology here in the board file. This will
99 * be used by the DDR3 init code in the SPL U-Boot version to configure
100 * the DDR3 controller.
102 static struct mv_ddr_topology_map board_topology_map = {
104 0x1, /* active interfaces */
105 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
106 { { { {0x1, 0, 0, 0},
111 SPEED_BIN_DDR_1600K, /* speed_bin */
112 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
113 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
114 MV_DDR_FREQ_800, /* frequency */
115 0, 0, /* cas_wl cas_l */
116 MV_DDR_TEMP_LOW, /* temperature */
117 MV_DDR_TIM_DEFAULT} }, /* timing */
118 BUS_MASK_32BIT, /* Busses mask */
119 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
120 { {0} }, /* raw spd data */
121 {0}, /* timing parameters */
122 { {0} }, /* electrical configuration */
123 {0,}, /* electrical parameters */
124 0x3, /* clock enable mask */
127 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
129 struct if_params *ifp = &board_topology_map.interface_params[0];
133 switch (cf_tlv_data.ram_size) {
136 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
139 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
143 /* Return the board topology as defined in the board code */
144 return &board_topology_map;
147 int board_early_init_f(void)
150 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
151 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
152 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
153 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
154 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
155 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
156 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
157 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
159 /* Set GPP Out value */
160 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
161 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
163 /* Set GPP Polarity */
164 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
165 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
167 /* Set GPP Out Enable */
168 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
169 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
176 /* Address of boot parameters */
177 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
179 /* Toggle GPIO41 to reset onboard switch and phy */
180 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
181 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
182 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
183 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
184 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
186 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
187 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
195 char *board = "Clearfog Pro";
196 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
197 board = "Clearfog Base";
200 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
201 board = cf_tlv_data.tlv_product_name[0];
203 printf("Board: SolidRun %s", board);
204 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
205 printf(", %s", cf_tlv_data.tlv_product_name[1]);
211 int board_eth_init(bd_t *bis)
213 cpu_eth_init(bis); /* Built in controller(s) come first */
214 return pci_eth_init(bis);
217 int board_late_init(void)
221 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
222 env_set("fdtfile", "armada-388-clearfog-base.dtb");
223 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
224 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
225 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
226 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
227 else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
228 env_set("fdtfile", "armada-388-clearfog-base.dtb");