1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
21 #include <linux/sizes.h>
23 #include <fsl_esdhc_imx.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
31 #include <usb/ehci-ci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
42 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
45 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
48 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
51 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
55 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
58 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
59 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
62 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
63 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
65 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
70 gd->ram_size = imx_ddr_size();
75 static iomux_v3_cfg_t const fec1_pads[] = {
76 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
79 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
80 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
83 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
86 /* LAN8720 PHY Reset */
87 MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
90 static iomux_v3_cfg_t const pwm_led_pads[] = {
91 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
92 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
93 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
96 #define PHY_RESET IMX_GPIO_NR(5, 9)
98 int board_eth_init(bd_t *bis)
100 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
102 unsigned char eth1addr[6];
104 /* just to get secound mac address */
105 imx_get_mac_from_fuse(1, eth1addr);
106 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
107 eth_env_set_enetaddr("eth1addr", eth1addr);
109 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
112 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
113 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
114 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
116 clrsetbits_le32(&iomuxc_regs->gpr[1],
117 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
118 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
119 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
120 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
122 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
127 gpio_request(PHY_RESET, "PHY-reset");
128 gpio_direction_output(PHY_RESET, 0);
130 gpio_set_value(PHY_RESET, 1);
133 ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
141 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
142 gpio_set_value(PHY_RESET, 0);
146 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
148 static struct i2c_pads_info i2c_pad_info1 = {
150 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
151 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
152 .gp = IMX_GPIO_NR(1, 0),
155 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
156 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
157 .gp = IMX_GPIO_NR(1, 1),
161 static struct pmic *pfuze_init(unsigned char i2cbus)
167 ret = power_pfuze100_init(i2cbus);
171 p = pmic_get("PFUZE100");
176 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
177 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
179 /* Set SW1AB stanby volage to 0.975V */
180 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
181 reg &= ~SW1x_STBY_MASK;
183 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
185 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
186 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
187 reg &= ~SW1xCONF_DVSSPEED_MASK;
188 reg |= SW1xCONF_DVSSPEED_4US;
189 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
191 /* Set SW1C standby voltage to 0.975V */
192 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
193 reg &= ~SW1x_STBY_MASK;
195 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
197 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
198 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
199 reg &= ~SW1xCONF_DVSSPEED_MASK;
200 reg |= SW1xCONF_DVSSPEED_4US;
201 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
206 static int pfuze_mode_init(struct pmic *p, u32 mode)
208 unsigned char offset, i, switch_num;
212 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
217 offset = PFUZE100_SW1CMODE;
218 } else if (id == 1) {
220 offset = PFUZE100_SW2MODE;
222 printf("Not supported, id=%d\n", id);
226 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
228 printf("Set SW1AB mode error!\n");
232 for (i = 0; i < switch_num - 1; i++) {
233 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
235 printf("Set switch 0x%x mode error!\n",
236 offset + i * SWITCH_SIZE);
244 int power_init_board(void)
249 p = pfuze_init(I2C_PMIC);
253 ret = pfuze_mode_init(p, APS_PFM);
260 #ifdef CONFIG_USB_EHCI_MX6
261 static iomux_v3_cfg_t const usb_otg_pads[] = {
263 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
264 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
266 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
269 static void setup_iomux_usb(void)
271 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
272 ARRAY_SIZE(usb_otg_pads));
275 int board_usb_phy_mode(int port)
278 return USB_INIT_HOST;
280 return usb_phy_mode(port);
284 #ifdef CONFIG_PWM_IMX
285 static int set_pwm_leds(void)
289 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
290 ARRAY_SIZE(pwm_led_pads));
291 /* enable backlight PWM 2, green LED */
292 ret = pwm_init(1, 0, 0);
295 /* duty cycle 200ns, period: 8000ns */
296 ret = pwm_config(1, 200, 8000);
303 /* enable backlight PWM 1, blue LED */
304 ret = pwm_init(0, 0, 0);
307 /* duty cycle 200ns, period: 8000ns */
308 ret = pwm_config(0, 200, 8000);
315 /* enable backlight PWM 6, red LED */
316 ret = pwm_init(5, 0, 0);
319 /* duty cycle 200ns, period: 8000ns */
320 ret = pwm_config(5, 200, 8000);
329 static int set_pwm_leds(void)
335 #define ADCx_HC0 0x00
337 #define ADCx_HS_C0 BIT(0)
339 #define ADCx_CFG 0x14
340 #define ADCx_CFG_SWMODE 0x308
342 #define ADCx_GC_CAL BIT(7)
344 static int read_adc(u32 *val)
347 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
349 /* use software mode */
350 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
352 /* start auto calibration */
353 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
354 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
358 /* start conversion */
359 writel(0, b + ADCx_HC0);
361 /* wait for conversion */
362 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
367 *val = readl(b + ADCx_R0);
371 printf("ADC failure (ret=%i)\n", ret);
372 unmap_physmem(b, MAP_NOCACHE);
376 #define VAL_UPPER 2498
377 #define VAL_LOWER 1550
379 static int set_pin_state(void)
384 ret = read_adc(&val);
388 if (val >= VAL_UPPER)
389 env_set("pin_state", "connected");
390 else if (val < VAL_UPPER && val > VAL_LOWER)
391 env_set("pin_state", "open");
393 env_set("pin_state", "button");
398 int board_late_init(void)
402 ret = set_pwm_leds();
406 ret = set_pin_state();
411 int board_early_init_f(void)
420 /* Address of boot parameters */
421 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
423 #ifdef CONFIG_SYS_I2C_MXC
424 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
432 puts("Board: VIN|ING 2000\n");