1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
21 #include <linux/sizes.h>
23 #include <fsl_esdhc_imx.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
31 #include <usb/ehci-ci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
42 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
45 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
48 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
51 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
55 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
58 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
59 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
62 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
63 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
65 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
70 gd->ram_size = imx_ddr_size();
75 static iomux_v3_cfg_t const pwm_led_pads[] = {
76 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
77 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
78 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
81 static int board_net_init(void)
83 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
84 unsigned char eth1addr[6];
87 /* just to get second mac address */
88 imx_get_mac_from_fuse(1, eth1addr);
89 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
90 eth_env_set_enetaddr("eth1addr", eth1addr);
93 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
94 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
95 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
97 clrsetbits_le32(&iomuxc_regs->gpr[1],
98 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
99 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
100 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
101 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
103 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
107 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
114 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
118 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
120 static struct i2c_pads_info i2c_pad_info1 = {
122 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
123 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
124 .gp = IMX_GPIO_NR(1, 0),
127 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
128 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
129 .gp = IMX_GPIO_NR(1, 1),
133 static struct pmic *pfuze_init(unsigned char i2cbus)
139 ret = power_pfuze100_init(i2cbus);
143 p = pmic_get("PFUZE100");
148 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
149 printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
151 /* Set SW1AB stanby volage to 0.975V */
152 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
153 reg &= ~SW1x_STBY_MASK;
155 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
157 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
158 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
159 reg &= ~SW1xCONF_DVSSPEED_MASK;
160 reg |= SW1xCONF_DVSSPEED_4US;
161 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
163 /* Set SW1C standby voltage to 0.975V */
164 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
165 reg &= ~SW1x_STBY_MASK;
167 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
169 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
170 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
171 reg &= ~SW1xCONF_DVSSPEED_MASK;
172 reg |= SW1xCONF_DVSSPEED_4US;
173 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
178 static int pfuze_mode_init(struct pmic *p, u32 mode)
180 unsigned char offset, i, switch_num;
184 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
189 offset = PFUZE100_SW1CMODE;
190 } else if (id == 1) {
192 offset = PFUZE100_SW2MODE;
194 printf("Not supported, id=%d\n", id);
198 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
200 printf("Set SW1AB mode error!\n");
204 for (i = 0; i < switch_num - 1; i++) {
205 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
207 printf("Set switch 0x%x mode error!\n",
208 offset + i * SWITCH_SIZE);
216 int power_init_board(void)
221 p = pfuze_init(I2C_PMIC);
225 ret = pfuze_mode_init(p, APS_PFM);
229 set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
230 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
235 #ifdef CONFIG_USB_EHCI_MX6
236 static iomux_v3_cfg_t const usb_otg_pads[] = {
238 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
239 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
241 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
244 static void setup_iomux_usb(void)
246 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
247 ARRAY_SIZE(usb_otg_pads));
250 int board_usb_phy_mode(int port)
253 return USB_INIT_HOST;
255 return usb_phy_mode(port);
259 #ifdef CONFIG_PWM_IMX
260 static int set_pwm_leds(void)
264 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
265 ARRAY_SIZE(pwm_led_pads));
266 /* enable backlight PWM 2, green LED */
267 ret = pwm_init(1, 0, 0);
270 /* duty cycle 200ns, period: 8000ns */
271 ret = pwm_config(1, 200, 8000);
278 /* enable backlight PWM 1, blue LED */
279 ret = pwm_init(0, 0, 0);
282 /* duty cycle 200ns, period: 8000ns */
283 ret = pwm_config(0, 200, 8000);
290 /* enable backlight PWM 6, red LED */
291 ret = pwm_init(5, 0, 0);
294 /* duty cycle 200ns, period: 8000ns */
295 ret = pwm_config(5, 200, 8000);
304 static int set_pwm_leds(void)
310 #define ADCx_HC0 0x00
312 #define ADCx_HS_C0 BIT(0)
314 #define ADCx_CFG 0x14
315 #define ADCx_CFG_SWMODE 0x308
317 #define ADCx_GC_CAL BIT(7)
319 static int read_adc(u32 *val)
322 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
324 /* use software mode */
325 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
327 /* start auto calibration */
328 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
329 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
333 /* start conversion */
334 writel(0, b + ADCx_HC0);
336 /* wait for conversion */
337 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
342 *val = readl(b + ADCx_R0);
346 printf("ADC failure (ret=%i)\n", ret);
347 unmap_physmem(b, MAP_NOCACHE);
351 #define VAL_UPPER 2498
352 #define VAL_LOWER 1550
354 static int set_pin_state(void)
359 ret = read_adc(&val);
363 if (val >= VAL_UPPER)
364 env_set("pin_state", "connected");
365 else if (val < VAL_UPPER && val > VAL_LOWER)
366 env_set("pin_state", "open");
368 env_set("pin_state", "button");
373 int board_late_init(void)
377 ret = set_pwm_leds();
381 ret = set_pin_state();
386 int board_early_init_f(void)
395 /* Address of boot parameters */
396 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
398 #ifdef CONFIG_SYS_I2C_MXC
399 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
402 return board_net_init();
407 puts("Board: VIN|ING 2000\n");
412 #define PCIE_PHY_PUP_REQ BIT(7)
414 void board_preboot_os(void)
416 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
417 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
419 /* Bring the PCI power domain up, so that old vendorkernel works. */
420 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
421 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
422 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
425 #ifdef CONFIG_SPL_BUILD
426 #include <linux/libfdt.h>
428 #include <asm/arch/mx6-ddr.h>
430 static iomux_v3_cfg_t const pcie_pads[] = {
431 MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
434 static iomux_v3_cfg_t const uart_pads[] = {
435 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
436 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
439 static iomux_v3_cfg_t const usdhc4_pads[] = {
440 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
441 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
442 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
443 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
444 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
445 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
446 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
447 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
448 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
449 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
452 static void vining2000_spl_setup_iomux_pcie(void)
454 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
457 static void vining2000_spl_setup_iomux_uart(void)
459 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
462 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
464 int board_mmc_init(bd_t *bis)
466 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
468 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
469 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
470 return fsl_esdhc_initialize(bis, &usdhc_cfg);
473 int board_mmc_getcd(struct mmc *mmc)
478 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
479 .dram_dqm0 = 0x00000028,
480 .dram_dqm1 = 0x00000028,
481 .dram_dqm2 = 0x00000028,
482 .dram_dqm3 = 0x00000028,
483 .dram_ras = 0x00000028,
484 .dram_cas = 0x00000028,
485 .dram_odt0 = 0x00000028,
486 .dram_odt1 = 0x00000028,
487 .dram_sdba2 = 0x00000000,
488 .dram_sdcke0 = 0x00003000,
489 .dram_sdcke1 = 0x00003000,
490 .dram_sdclk_0 = 0x00000030,
491 .dram_sdqs0 = 0x00000028,
492 .dram_sdqs1 = 0x00000028,
493 .dram_sdqs2 = 0x00000028,
494 .dram_sdqs3 = 0x00000028,
495 .dram_reset = 0x00000028,
498 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
499 .grp_addds = 0x00000028,
500 .grp_b0ds = 0x00000028,
501 .grp_b1ds = 0x00000028,
502 .grp_b2ds = 0x00000028,
503 .grp_b3ds = 0x00000028,
504 .grp_ctlds = 0x00000028,
505 .grp_ddr_type = 0x000c0000,
506 .grp_ddrmode = 0x00020000,
507 .grp_ddrmode_ctl = 0x00020000,
508 .grp_ddrpke = 0x00000000,
511 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
512 .p0_mpwldectrl0 = 0x0022001C,
513 .p0_mpwldectrl1 = 0x001F001A,
514 .p0_mpdgctrl0 = 0x01380134,
515 .p0_mpdgctrl1 = 0x0124011C,
516 .p0_mprddlctl = 0x42404444,
517 .p0_mpwrdlctl = 0x36383C38,
520 static struct mx6_ddr3_cfg mem_ddr = {
533 static void ccgr_init(void)
535 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
537 writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
538 writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
539 writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
540 writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
541 writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
542 writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
543 writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
546 static void vining2000_spl_dram_init(void)
548 struct mx6_ddr_sysinfo sysinfo = {
549 .dsize = mem_ddr.width / 32,
553 .rtt_wr = 1, /* RTT_wr = RZQ/4 */
554 .rtt_nom = 1, /* RTT_Nom = RZQ/4 */
555 .walat = 1, /* Write additional latency */
556 .ralat = 5, /* Read additional latency */
557 .mif3_mode = 3, /* Command prediction working mode */
558 .bi_on = 1, /* Bank interleaving enabled */
559 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
560 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
561 .ddr_type = DDR_TYPE_DDR3,
562 .refsel = 1, /* Refresh cycles at 32KHz */
563 .refr = 7, /* 8 refresh commands per refresh cycle */
566 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
567 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
569 /* Perform DDR DRAM calibration */
571 mmdc_do_write_level_calibration(&sysinfo);
572 mmdc_do_dqs_calibration(&sysinfo);
575 void board_init_f(ulong dummy)
577 /* setup AIPS and disable watchdog */
583 vining2000_spl_setup_iomux_pcie();
584 vining2000_spl_setup_iomux_uart();
589 /* reset the PCIe device */
590 gpio_set_value(IMX_GPIO_NR(4, 6), 1);
592 gpio_set_value(IMX_GPIO_NR(4, 6), 0);
594 /* UART clocks enabled and gd valid - init serial console */
595 preloader_console_init();
597 /* DDR initialization */
598 vining2000_spl_dram_init();
601 memset(__bss_start, 0, __bss_end - __bss_start);
603 /* load/boot image from boot device */
604 board_init_r(NULL, 0);