1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <linux/sizes.h>
21 #include <environment.h>
22 #include <fsl_esdhc.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
30 #include <usb/ehci-ci.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
41 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
44 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
46 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
47 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
50 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
54 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
57 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
58 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
61 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
62 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
64 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
69 gd->ram_size = imx_ddr_size();
74 static iomux_v3_cfg_t const uart1_pads[] = {
75 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
79 static iomux_v3_cfg_t const fec1_pads[] = {
80 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
83 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
84 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
87 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
90 /* LAN8720 PHY Reset */
91 MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
94 static iomux_v3_cfg_t const pwm_led_pads[] = {
95 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
96 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
97 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
100 static void setup_iomux_uart(void)
102 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
105 #define PHY_RESET IMX_GPIO_NR(5, 9)
107 int board_eth_init(bd_t *bis)
109 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
111 unsigned char eth1addr[6];
113 /* just to get secound mac address */
114 imx_get_mac_from_fuse(1, eth1addr);
115 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
116 eth_env_set_enetaddr("eth1addr", eth1addr);
118 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
121 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
122 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
123 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
125 clrsetbits_le32(&iomuxc_regs->gpr[1],
126 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
127 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
128 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
129 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
131 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
136 gpio_direction_output(PHY_RESET, 0);
138 gpio_set_value(PHY_RESET, 1);
141 ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
149 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
150 gpio_set_value(PHY_RESET, 0);
154 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
156 static struct i2c_pads_info i2c_pad_info1 = {
158 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
159 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
160 .gp = IMX_GPIO_NR(1, 0),
163 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
164 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
165 .gp = IMX_GPIO_NR(1, 1),
169 static struct pmic *pfuze_init(unsigned char i2cbus)
175 ret = power_pfuze100_init(i2cbus);
179 p = pmic_get("PFUZE100");
184 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
185 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
187 /* Set SW1AB stanby volage to 0.975V */
188 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
189 reg &= ~SW1x_STBY_MASK;
191 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
193 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
194 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
195 reg &= ~SW1xCONF_DVSSPEED_MASK;
196 reg |= SW1xCONF_DVSSPEED_4US;
197 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
199 /* Set SW1C standby voltage to 0.975V */
200 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
201 reg &= ~SW1x_STBY_MASK;
203 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
205 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
206 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
207 reg &= ~SW1xCONF_DVSSPEED_MASK;
208 reg |= SW1xCONF_DVSSPEED_4US;
209 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
214 static int pfuze_mode_init(struct pmic *p, u32 mode)
216 unsigned char offset, i, switch_num;
220 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
225 offset = PFUZE100_SW1CMODE;
226 } else if (id == 1) {
228 offset = PFUZE100_SW2MODE;
230 printf("Not supported, id=%d\n", id);
234 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
236 printf("Set SW1AB mode error!\n");
240 for (i = 0; i < switch_num - 1; i++) {
241 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
243 printf("Set switch 0x%x mode error!\n",
244 offset + i * SWITCH_SIZE);
252 int power_init_board(void)
257 p = pfuze_init(I2C_PMIC);
261 ret = pfuze_mode_init(p, APS_PFM);
268 #ifdef CONFIG_USB_EHCI_MX6
269 static iomux_v3_cfg_t const usb_otg_pads[] = {
271 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
272 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
274 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
277 static void setup_iomux_usb(void)
279 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
280 ARRAY_SIZE(usb_otg_pads));
283 int board_usb_phy_mode(int port)
286 return USB_INIT_HOST;
288 return usb_phy_mode(port);
292 #ifdef CONFIG_PWM_IMX
293 static int set_pwm_leds(void)
297 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
298 ARRAY_SIZE(pwm_led_pads));
299 /* enable backlight PWM 2, green LED */
300 ret = pwm_init(1, 0, 0);
303 /* duty cycle 200ns, period: 8000ns */
304 ret = pwm_config(1, 200, 8000);
311 /* enable backlight PWM 1, blue LED */
312 ret = pwm_init(0, 0, 0);
315 /* duty cycle 200ns, period: 8000ns */
316 ret = pwm_config(0, 200, 8000);
323 /* enable backlight PWM 6, red LED */
324 ret = pwm_init(5, 0, 0);
327 /* duty cycle 200ns, period: 8000ns */
328 ret = pwm_config(5, 200, 8000);
337 static int set_pwm_leds(void)
343 #define ADCx_HC0 0x00
345 #define ADCx_HS_C0 BIT(0)
347 #define ADCx_CFG 0x14
348 #define ADCx_CFG_SWMODE 0x308
350 #define ADCx_GC_CAL BIT(7)
352 static int read_adc(u32 *val)
355 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
357 /* use software mode */
358 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
360 /* start auto calibration */
361 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
362 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
366 /* start conversion */
367 writel(0, b + ADCx_HC0);
369 /* wait for conversion */
370 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
375 *val = readl(b + ADCx_R0);
379 printf("ADC failure (ret=%i)\n", ret);
380 unmap_physmem(b, MAP_NOCACHE);
384 #define VAL_UPPER 2498
385 #define VAL_LOWER 1550
387 static int set_pin_state(void)
392 ret = read_adc(&val);
396 if (val >= VAL_UPPER)
397 env_set("pin_state", "connected");
398 else if (val < VAL_UPPER && val > VAL_LOWER)
399 env_set("pin_state", "open");
401 env_set("pin_state", "button");
406 int board_late_init(void)
410 ret = set_pwm_leds();
414 ret = set_pin_state();
419 int board_early_init_f(void)
430 /* Address of boot parameters */
431 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
433 #ifdef CONFIG_SYS_I2C_MXC
434 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
442 puts("Board: VIN|ING 2000\n");