3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 * Copyright 2008 Freescale Semiconductor, Inc.
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 struct fsl_e_tlb_entry tlb_table[] = {
33 /* TLB 0 - for temp stack in cache */
34 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
35 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
44 MAS3_SX|MAS3_SW|MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
49 * TLB 0, 1: 128M Non-cacheable, guarded
50 * 0xf8000000 128M FLASH
51 * Out of reset this entry is only 4K.
53 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 1, BOOKE_PAGESZ_64M, 1),
56 SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 0, BOOKE_PAGESZ_64M, 1),
61 * TLB 2: 256M Non-cacheable, guarded
62 * 0x80000000 256M PCI1 MEM First half
64 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
65 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
66 0, 2, BOOKE_PAGESZ_256M, 1),
69 * TLB 3: 256M Non-cacheable, guarded
70 * 0x90000000 256M PCI1 MEM Second half
72 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 3, BOOKE_PAGESZ_256M, 1),
77 * TLB 4: 256M Non-cacheable, guarded
78 * 0xc0000000 256M Rapid IO MEM First half
80 SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
81 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 0, 4, BOOKE_PAGESZ_256M, 1),
85 * TLB 5: 256M Non-cacheable, guarded
86 * 0xd0000000 256M Rapid IO MEM Second half
88 SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 0, 5, BOOKE_PAGESZ_256M, 1),
93 * TLB 6: 64M Non-cacheable, guarded
94 * 0xe000_0000 1M CCSRBAR
95 * 0xe200_0000 16M PCI1 IO
97 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
98 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
99 0, 6, BOOKE_PAGESZ_64M, 1),
102 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
103 * 0x00000000 512M DDR System memory
104 * Without SPD EEPROM configured DDR, this must be setup manually.
105 * Make sure the TLB count at the top of this table is correct.
106 * Likely it needs to be increased by two for these entries.
108 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
109 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
110 0, 7, BOOKE_PAGESZ_256M, 1),
112 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
113 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
114 0, 8, BOOKE_PAGESZ_256M, 1),
117 int num_tlb_entries = ARRAY_SIZE(tlb_table);