1 // SPDX-License-Identifier: GPL-2.0+
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
14 #include <clock_legacy.h>
17 #include <asm/processor.h>
18 #include <asm/immap_85xx.h>
21 #include <linux/libfdt.h>
22 #include <fdt_support.h>
27 #include "upm_table.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 extern flash_info_t flash_info[]; /* FLASH chips info */
32 extern GraphicDevice mb862xx;
34 void local_bus_init (void);
35 ulong flash_get_size (ulong base, int banknum);
39 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
42 int i = env_get_f("serial#", buf, sizeof(buf));
47 puts("Board: Socrates");
54 #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
55 /* Check the PCI_clk sel bit */
56 if (in_be32(&gur->porpllsr) & (1<<15)) {
58 f = CONFIG_SYS_CLK_FREQ;
61 f = CONFIG_PCI_CLK_FREQ;
63 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
65 printf ("PCI1: disabled\n");
69 * Initialize local bus.
75 int misc_init_r (void)
78 * Adjust flash start and offset to detected values
80 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
81 gd->bd->bi_flashoffset = 0;
84 * Check if boot FLASH isn't max size
86 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
87 set_lbc_or(0, gd->bd->bi_flashstart |
88 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
89 set_lbc_br(0, gd->bd->bi_flashstart |
90 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
93 * Re-check to get correct base address
95 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
99 * Check if only one FLASH bank is available
101 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
106 * Re-do flash protection upon new addresses
108 flash_protect (FLAG_PROTECT_CLEAR,
109 gd->bd->bi_flashstart, 0xffffffff,
110 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
112 /* Monitor protection ON by default */
113 flash_protect (FLAG_PROTECT_SET,
114 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
115 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
117 /* Environment protection ON by default */
118 flash_protect (FLAG_PROTECT_SET,
120 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
121 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
123 /* Redundant environment protection ON by default */
124 flash_protect (FLAG_PROTECT_SET,
125 CONFIG_ENV_ADDR_REDUND,
126 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
127 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
130 #if defined(CONFIG_DM_PCI)
138 * Initialize Local Bus
140 void local_bus_init (void)
142 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
143 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
147 uint lcrr = CONFIG_SYS_LBC_LCRR;
149 get_sys_info (&sysinfo);
150 clkdiv = lbc->lcrr & LCRR_CLKDIV;
151 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
153 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
155 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
157 lcrr |= LCRR_DBYP; /* DLL Bypass */
159 out_be32 (&lbc->lcrr, lcrr);
160 asm ("sync;isync;msync");
162 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
163 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
164 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
165 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
167 /* Init UPMA for FPGA access */
168 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
169 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
171 /* Init UPMB for Lime controller access */
172 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
173 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
176 #ifdef CONFIG_BOARD_EARLY_INIT_R
177 int board_early_init_r (void)
179 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
181 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
182 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
183 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
185 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
189 #endif /* CONFIG_BOARD_EARLY_INIT_R */
191 #ifdef CONFIG_OF_BOARD_SETUP
192 int ft_board_setup(void *blob, bd_t *bd)
197 ft_cpu_setup(blob, bd);
199 /* Fixup NOR FLASH mapping */
200 val[i++] = 0; /* chip select number */
201 val[i++] = 0; /* always 0 */
202 val[i++] = gd->bd->bi_flashstart;
203 val[i++] = gd->bd->bi_flashsize;
205 #if defined(CONFIG_VIDEO_MB862xx)
206 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
207 /* Fixup LIME mapping */
208 val[i++] = 2; /* chip select number */
209 val[i++] = 0; /* always 0 */
210 val[i++] = CONFIG_SYS_LIME_BASE;
211 val[i++] = CONFIG_SYS_LIME_SIZE;
215 /* Fixup FPGA mapping */
216 val[i++] = 3; /* chip select number */
217 val[i++] = 0; /* always 0 */
218 val[i++] = CONFIG_SYS_FPGA_BASE;
219 val[i++] = CONFIG_SYS_FPGA_SIZE;
221 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
222 val, i * sizeof(u32), 1);
224 printf("Unable to update localbus ranges, err=%s\n",
229 #endif /* CONFIG_OF_BOARD_SETUP */
231 #if defined(CONFIG_OF_SEPARATE)
232 void *board_fdt_blob_setup(void)
236 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
237 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
238 printf("DTB is not passed via %x\n", (u32)fw_dtb);
246 int get_serial_clock(void)