Merge branch 'master' of /home/wd/git/u-boot/custodians
[oweals/u-boot.git] / board / socrates / ddr.c
1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #include <common.h>
10 #include <i2c.h>
11
12 #include <asm/fsl_ddr_sdram.h>
13
14 static void
15 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
16 {
17         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
18 }
19
20 unsigned int fsl_ddr_get_mem_data_rate(void)
21 {
22         return get_ddr_freq(0);
23 }
24
25 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
26                       unsigned int ctrl_num)
27 {
28         unsigned int i;
29
30         if (ctrl_num) {
31                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
32                 return;
33         }
34
35         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
36                 get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
37         }
38 }
39
40 void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
41 {
42         /*
43          * Factors to consider for clock adjust:
44          *      - number of chips on bus
45          *      - position of slot
46          *      - DDR1 vs. DDR2?
47          *      - ???
48          *
49          * This needs to be determined on a board-by-board basis.
50          *      0110    3/4 cycle late
51          *      0111    7/8 cycle late
52          */
53         popts->clk_adjust = 7;
54
55         /*
56          * Factors to consider for CPO:
57          *      - frequency
58          *      - ddr1 vs. ddr2
59          */
60         popts->cpo_override = 10;
61
62         /*
63          * Factors to consider for write data delay:
64          *      - number of DIMMs
65          *
66          * 1 = 1/4 clock delay
67          * 2 = 1/2 clock delay
68          * 3 = 3/4 clock delay
69          * 4 = 1   clock delay
70          * 5 = 5/4 clock delay
71          * 6 = 3/2 clock delay
72          */
73         popts->write_data_delay = 3;
74
75         /*
76          * Factors to consider for half-strength driver enable:
77          *      - number of DIMMs installed
78          */
79         popts->half_strength_driver_enable = 0;
80 }