2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * Achim Ehrlich <aehrlich@taskit.de>
7 * taskit GmbH <www.taskit.de>
10 * Markus Hubig <mhubig@imko.de>
11 * IMKO GmbH <www.imko.de>
13 * Heiko Schocher <hs@denx.de>
14 * DENX Software Engineering GmbH
16 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/arch/at91sam9_sdramc.h>
22 #include <asm/arch/at91sam9260_matrix.h>
23 #include <asm/arch/at91sam9_smc.h>
24 #include <asm/arch/at91_common.h>
25 #include <asm/arch/at91_pmc.h>
26 #include <asm/arch/at91_spi.h>
28 #include <asm/arch/clk.h>
29 #include <asm/arch/gpio.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 static void smartweb_nand_hw_init(void)
40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
44 /* Assign CS3 to NAND/SmartMedia Interface */
45 csa = readl(&matrix->ebicsa);
46 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
47 writel(csa, &matrix->ebicsa);
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 AT91_SMC_MODE_TDF_CYCLE(2),
62 /* Configure RDY/BSY */
63 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
65 /* Enable NandFlash */
66 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
70 static void smartweb_macb_hw_init(void)
72 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
74 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
75 at91_set_gpio_output(AT91_PIN_PA26, 0);
79 * RXDV (PA17) => PHY normal mode (not Test mode)
80 * ERX0 (PA14) => PHY ADDR0
81 * ERX1 (PA15) => PHY ADDR1
82 * ERX2 (PA25) => PHY ADDR2
83 * ERX3 (PA26) => PHY ADDR3
84 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
86 * PHY has internal pull-down
88 writel(pin_to_mask(AT91_PIN_PA14) |
89 pin_to_mask(AT91_PIN_PA15) |
90 pin_to_mask(AT91_PIN_PA17) |
91 pin_to_mask(AT91_PIN_PA25) |
92 pin_to_mask(AT91_PIN_PA26) |
93 pin_to_mask(AT91_PIN_PA28) |
94 pin_to_mask(AT91_PIN_PA29),
99 /* Re-enable pull-up */
100 writel(pin_to_mask(AT91_PIN_PA14) |
101 pin_to_mask(AT91_PIN_PA15) |
102 pin_to_mask(AT91_PIN_PA17) |
103 pin_to_mask(AT91_PIN_PA25) |
104 pin_to_mask(AT91_PIN_PA26) |
105 pin_to_mask(AT91_PIN_PA28) |
106 pin_to_mask(AT91_PIN_PA29),
109 /* Initialize EMAC=MACB hardware */
112 #endif /* CONFIG_MACB */
114 #ifdef CONFIG_USB_GADGET_AT91
115 #include <linux/usb/at91_udc.h>
117 void at91_udp_hw_init(void)
119 at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
122 writel(get_pllb_init(), &pmc->pllbr);
123 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
126 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
127 at91_periph_clk_enable(ATMEL_ID_UDP);
129 writel(AT91SAM926x_PMC_UDP, &pmc->scer);
132 struct at91_udc_data board_udc_data = {
133 .baseaddr = ATMEL_BASE_UDP0,
137 int board_early_init_f(void)
139 /* enable this here, as we have SPL without serial support */
140 at91_seriald_hw_init();
147 at91_set_gpio_output(AT91_PIN_PC6, 0);
148 at91_set_gpio_output(AT91_PIN_PC7, 1);
150 at91_set_gpio_output(AT91_PIN_PC8, 0);
151 at91_set_gpio_output(AT91_PIN_PC9, 0);
153 at91_set_gpio_output(AT91_PIN_PC10, 0);
154 at91_set_gpio_output(AT91_PIN_PC11, 1);
156 #ifdef CONFIG_USB_GADGET_AT91
158 at91_udc_probe(&board_udc_data);
161 /* Adress of boot parameters */
162 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
164 smartweb_nand_hw_init();
166 smartweb_macb_hw_init();
173 gd->ram_size = get_ram_size(
174 (void *)CONFIG_SYS_SDRAM_BASE,
175 CONFIG_SYS_SDRAM_SIZE);
180 int board_eth_init(bd_t *bis)
182 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
184 #endif /* CONFIG_MACB */
186 #if defined(CONFIG_SPL_BUILD)
189 #include <spi_flash.h>
191 void matrix_init(void)
193 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
195 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
196 | AT91_MATRIX_SLOT_CYCLE_(0x40),
200 void spl_board_init(void)
202 /* power LED orange */
203 at91_set_gpio_output(AT91_PIN_PC6, 1);
204 at91_set_gpio_output(AT91_PIN_PC7, 1);
205 /* alarm LED orange */
206 at91_set_gpio_output(AT91_PIN_PC8, 1);
207 at91_set_gpio_output(AT91_PIN_PC9, 1);
209 at91_set_gpio_output(AT91_PIN_PC10, 0);
210 at91_set_gpio_output(AT91_PIN_PC11, 1);
212 smartweb_nand_hw_init();
213 at91_set_gpio_input(AT91_PIN_PA28, 1);
214 at91_set_gpio_input(AT91_PIN_PA29, 1);
216 /* check if both button are pressed */
217 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
218 at91_get_gpio_value(AT91_PIN_PA29) == 0) {
219 smartweb_nand_hw_init();
221 spl_nand_erase_one(0, 0);
225 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
226 | AT91_SDRAMC_CAS_2 \
227 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
228 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
229 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
230 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
234 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
235 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
236 struct sdramc_reg setting;
238 setting.cr = SDRAM_BASE_CONF;
239 setting.mdr = AT91_SDRAMC_MD_SDRAM;
240 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
243 * I write here directly in this register, because this
244 * approach is smaller than calling at91_set_a_periph() in a
245 * for loop. This saved me 96 bytes.
247 writel(0xffff0000, &port->pdr);
249 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
250 sdramc_initialize(ATMEL_BASE_CS1, &setting);