1 // SPDX-License-Identifier: GPL-2.0+
3 * Board functions for TI AM335X based rut board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * u-boot:/board/ti/am335x/board.c
10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/omap.h>
24 #include <asm/arch/ddr_defs.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
38 #include "../common/factoryset.h"
39 #include "../../../drivers/video/da8xx-fb.h"
42 * Read header information from EEPROM into global structure.
44 static int read_eeprom(void)
49 #ifdef CONFIG_SPL_BUILD
50 static void board_init_ddr(void)
52 struct emif_regs rut_ddr3_emif_reg_data = {
53 .sdram_config = 0x61C04AB2,
54 .sdram_tim1 = 0x0888A39B,
55 .sdram_tim2 = 0x26337FDA,
56 .sdram_tim3 = 0x501F830F,
57 .emif_ddr_phy_ctlr_1 = 0x6,
58 .zq_config = 0x50074BE4,
62 struct ddr_data rut_ddr3_data = {
63 .datardsratio0 = 0x3b,
64 .datawdsratio0 = 0x85,
65 .datafwsratio0 = 0x100,
66 .datawrsratio0 = 0xc1,
69 struct cmd_control rut_ddr3_cmd_ctrl_data = {
78 const struct ctrl_ioregs ioregs = {
79 .cm0ioctl = RUT_IOCTRL_VAL,
80 .cm1ioctl = RUT_IOCTRL_VAL,
81 .cm2ioctl = RUT_IOCTRL_VAL,
82 .dt0ioctl = RUT_IOCTRL_VAL,
83 .dt1ioctl = RUT_IOCTRL_VAL,
86 config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
87 &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
90 static int request_and_pulse_reset(int gpio, const char *name)
93 const int delay_us = 2000; /* 2ms */
95 ret = gpio_request(gpio, name);
97 printf("%s: Unable to request %s\n", __func__, name);
101 ret = gpio_direction_output(gpio, 0);
103 printf("%s: Unable to set %s as output\n", __func__, name);
109 gpio_set_value(gpio, 1);
119 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
120 #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
121 #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
122 #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
124 #define REQUEST_AND_PULSE_RESET(N) \
125 request_and_pulse_reset(N, #N);
127 static void spl_siemens_board_init(void)
129 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
130 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
131 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
133 #endif /* if def CONFIG_SPL_BUILD */
135 #if defined(CONFIG_DRIVER_TI_CPSW)
136 static void cpsw_control(int enabled)
138 /* VTP can be added here */
143 static struct cpsw_slave_data cpsw_slaves[] = {
145 .slave_reg_ofs = 0x208,
146 .sliver_reg_ofs = 0xd80,
148 .phy_if = PHY_INTERFACE_MODE_RMII,
151 .slave_reg_ofs = 0x308,
152 .sliver_reg_ofs = 0xdc0,
154 .phy_if = PHY_INTERFACE_MODE_RMII,
158 static struct cpsw_platform_data cpsw_data = {
159 .mdio_base = CPSW_MDIO_BASE,
160 .cpsw_base = CPSW_BASE,
163 .cpdma_reg_ofs = 0x800,
165 .slave_data = cpsw_slaves,
166 .ale_reg_ofs = 0xd00,
168 .host_port_reg_ofs = 0x108,
169 .hw_stats_reg_ofs = 0x900,
170 .bd_ram_ofs = 0x2000,
171 .mac_control = (1 << 5),
172 .control = cpsw_control,
174 .version = CPSW_CTRL_VERSION_2,
177 #if defined(CONFIG_DRIVER_TI_CPSW) || \
178 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
179 int board_eth_init(bd_t *bis)
181 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
185 #ifndef CONFIG_SPL_BUILD
186 factoryset_env_set();
189 /* Set rgmii mode and enable rmii clock to be sourced from chip */
190 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
192 rv = cpsw_register(&cpsw_data);
194 printf("Error %d registering CPSW switch\n", rv);
199 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
200 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
202 #if defined(CONFIG_HW_WATCHDOG)
203 static bool hw_watchdog_init_done;
204 static int hw_watchdog_trigger_level;
206 void hw_watchdog_reset(void)
208 if (!hw_watchdog_init_done)
211 hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
212 gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
215 void hw_watchdog_init(void)
217 gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
218 gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
222 hw_watchdog_init_done = 1;
224 #endif /* defined(CONFIG_HW_WATCHDOG) */
226 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
227 static struct da8xx_panel lcd_panels[] = {
228 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
230 .name = "KWH043MC17-F01",
233 .hfp = 50, /* no spec, "don't care" values */
239 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
242 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
244 .name = "KWH043ST20-F01",
247 .hfp = 50, /* no spec, "don't care" values */
253 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
256 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
258 .name = "MI0430VT-1",
261 .hfp = 50, /* no spec, "don't care" values */
267 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
272 static const struct display_panel disp_panels[] = {
293 static const struct lcd_ctrl_config lcd_cfgs[] = {
304 .invert_line_clock = 1,
305 .invert_frm_clock = 1,
320 .invert_line_clock = 1,
321 .invert_frm_clock = 1,
336 .invert_line_clock = 1,
337 .invert_frm_clock = 1,
345 /* no console on this board */
346 int board_cfb_skip(void)
351 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
352 #define PLL_GET_N(v) (v & 0x7f)
354 static struct dpll_regs dpll_lcd_regs = {
355 .cm_clkmode_dpll = CM_WKUP + 0x98,
356 .cm_idlest_dpll = CM_WKUP + 0x48,
357 .cm_clksel_dpll = CM_WKUP + 0x54,
360 static int get_clk(struct dpll_regs *dpll_regs)
366 val = readl(dpll_regs->cm_clksel_dpll);
369 f = (m * V_OSCK) / n;
376 return get_clk(&dpll_lcd_regs);
379 static int conf_disp_pll(int m, int n)
381 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
382 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
383 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
384 struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
387 u32 *const clk_domains[] = {
391 u32 *const clk_modules_explicit_en[] = {
393 &cmper->lcdcclkstctrl,
397 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
399 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
401 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
402 writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
403 writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
404 writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
405 &cmwkup->clkmoddplldisp); /* 0x98 */
410 static int set_gpio(int gpio, int state)
412 gpio_request(gpio, "temp");
413 gpio_direction_output(gpio, state);
414 gpio_set_value(gpio, state);
419 static int enable_lcd(void)
421 unsigned char buf[1];
423 set_gpio(BOARD_LCD_RESET, 0);
425 set_gpio(BOARD_LCD_RESET, 1);
429 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
433 i2c_write(0x24, 0x7, 1, buf, 1);
435 i2c_write(0x24, 0x8, 1, buf, 1);
439 int arch_early_init_r(void)
445 static int board_video_init(void)
448 int anzdisp = ARRAY_SIZE(lcd_panels);
451 for (i = 0; i < anzdisp; i++) {
452 if (strncmp((const char *)factory_dat.disp_name,
454 strlen((const char *)factory_dat.disp_name)) == 0) {
455 printf("DISPLAY: %s\n", factory_dat.disp_name);
461 printf("%s: %s not found, using default %s\n", __func__,
462 factory_dat.disp_name, lcd_panels[i].name);
464 conf_disp_pll(24, 1);
465 da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
466 lcd_cfgs[display].bpp);
470 #endif /* ifdef CONFIG_VIDEO */
472 #ifdef CONFIG_BOARD_LATE_INIT
473 int board_late_init(void)
476 char tmp[2 * MAX_STRING_LENGTH + 2];
478 omap_nand_switch_ecc(1, 8);
480 if (factory_dat.asn[0] != 0)
481 sprintf(tmp, "%s_%s", factory_dat.asn,
482 factory_dat.comp_version);
484 strcpy(tmp, "QMX7.E38_4.0");
486 ret = env_set("boardid", tmp);
488 printf("error setting board id\n");
494 #include "../common/board.c"