1 // SPDX-License-Identifier: GPL-2.0+
3 * Board functions for TI AM335X based rut board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * u-boot:/board/ti/am335x/board.c
10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/omap.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
36 #include "../../../drivers/video/da8xx-fb.h"
39 * Read header information from EEPROM into global structure.
41 static int read_eeprom(void)
46 #ifdef CONFIG_SPL_BUILD
47 static void board_init_ddr(void)
49 struct emif_regs rut_ddr3_emif_reg_data = {
50 .sdram_config = 0x61C04AB2,
51 .sdram_tim1 = 0x0888A39B,
52 .sdram_tim2 = 0x26337FDA,
53 .sdram_tim3 = 0x501F830F,
54 .emif_ddr_phy_ctlr_1 = 0x6,
55 .zq_config = 0x50074BE4,
59 struct ddr_data rut_ddr3_data = {
60 .datardsratio0 = 0x3b,
61 .datawdsratio0 = 0x85,
62 .datafwsratio0 = 0x100,
63 .datawrsratio0 = 0xc1,
66 struct cmd_control rut_ddr3_cmd_ctrl_data = {
75 const struct ctrl_ioregs ioregs = {
76 .cm0ioctl = RUT_IOCTRL_VAL,
77 .cm1ioctl = RUT_IOCTRL_VAL,
78 .cm2ioctl = RUT_IOCTRL_VAL,
79 .dt0ioctl = RUT_IOCTRL_VAL,
80 .dt1ioctl = RUT_IOCTRL_VAL,
83 config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
84 &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
87 static int request_and_pulse_reset(int gpio, const char *name)
90 const int delay_us = 2000; /* 2ms */
92 ret = gpio_request(gpio, name);
94 printf("%s: Unable to request %s\n", __func__, name);
98 ret = gpio_direction_output(gpio, 0);
100 printf("%s: Unable to set %s as output\n", __func__, name);
106 gpio_set_value(gpio, 1);
116 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
117 #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
118 #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
119 #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
121 #define REQUEST_AND_PULSE_RESET(N) \
122 request_and_pulse_reset(N, #N);
124 static void spl_siemens_board_init(void)
126 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
127 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
128 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
130 #endif /* if def CONFIG_SPL_BUILD */
132 #if defined(CONFIG_DRIVER_TI_CPSW)
133 static void cpsw_control(int enabled)
135 /* VTP can be added here */
140 static struct cpsw_slave_data cpsw_slaves[] = {
142 .slave_reg_ofs = 0x208,
143 .sliver_reg_ofs = 0xd80,
145 .phy_if = PHY_INTERFACE_MODE_RMII,
148 .slave_reg_ofs = 0x308,
149 .sliver_reg_ofs = 0xdc0,
151 .phy_if = PHY_INTERFACE_MODE_RMII,
155 static struct cpsw_platform_data cpsw_data = {
156 .mdio_base = CPSW_MDIO_BASE,
157 .cpsw_base = CPSW_BASE,
160 .cpdma_reg_ofs = 0x800,
162 .slave_data = cpsw_slaves,
163 .ale_reg_ofs = 0xd00,
165 .host_port_reg_ofs = 0x108,
166 .hw_stats_reg_ofs = 0x900,
167 .bd_ram_ofs = 0x2000,
168 .mac_control = (1 << 5),
169 .control = cpsw_control,
171 .version = CPSW_CTRL_VERSION_2,
174 #if defined(CONFIG_DRIVER_TI_CPSW) || \
175 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
176 int board_eth_init(bd_t *bis)
178 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
182 #ifndef CONFIG_SPL_BUILD
183 factoryset_env_set();
186 /* Set rgmii mode and enable rmii clock to be sourced from chip */
187 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
189 rv = cpsw_register(&cpsw_data);
191 printf("Error %d registering CPSW switch\n", rv);
196 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
197 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
199 #if defined(CONFIG_HW_WATCHDOG)
200 static bool hw_watchdog_init_done;
201 static int hw_watchdog_trigger_level;
203 void hw_watchdog_reset(void)
205 if (!hw_watchdog_init_done)
208 hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
209 gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
212 void hw_watchdog_init(void)
214 gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
215 gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
219 hw_watchdog_init_done = 1;
221 #endif /* defined(CONFIG_HW_WATCHDOG) */
223 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
224 static struct da8xx_panel lcd_panels[] = {
225 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
227 .name = "KWH043MC17-F01",
230 .hfp = 50, /* no spec, "don't care" values */
236 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
239 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
241 .name = "KWH043ST20-F01",
244 .hfp = 50, /* no spec, "don't care" values */
250 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
253 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
255 .name = "MI0430VT-1",
258 .hfp = 50, /* no spec, "don't care" values */
264 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
269 static const struct display_panel disp_panels[] = {
290 static const struct lcd_ctrl_config lcd_cfgs[] = {
301 .invert_line_clock = 1,
302 .invert_frm_clock = 1,
317 .invert_line_clock = 1,
318 .invert_frm_clock = 1,
333 .invert_line_clock = 1,
334 .invert_frm_clock = 1,
342 /* no console on this board */
343 int board_cfb_skip(void)
348 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
349 #define PLL_GET_N(v) (v & 0x7f)
351 static struct dpll_regs dpll_lcd_regs = {
352 .cm_clkmode_dpll = CM_WKUP + 0x98,
353 .cm_idlest_dpll = CM_WKUP + 0x48,
354 .cm_clksel_dpll = CM_WKUP + 0x54,
357 static int get_clk(struct dpll_regs *dpll_regs)
363 val = readl(dpll_regs->cm_clksel_dpll);
366 f = (m * V_OSCK) / n;
373 return get_clk(&dpll_lcd_regs);
376 static int conf_disp_pll(int m, int n)
378 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
379 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
380 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
381 struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
384 u32 *const clk_domains[] = {
388 u32 *const clk_modules_explicit_en[] = {
390 &cmper->lcdcclkstctrl,
394 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
396 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
398 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
399 writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
400 writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
401 writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
402 &cmwkup->clkmoddplldisp); /* 0x98 */
407 static int set_gpio(int gpio, int state)
409 gpio_request(gpio, "temp");
410 gpio_direction_output(gpio, state);
411 gpio_set_value(gpio, state);
416 static int enable_lcd(void)
418 unsigned char buf[1];
420 set_gpio(BOARD_LCD_RESET, 0);
422 set_gpio(BOARD_LCD_RESET, 1);
426 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
430 i2c_write(0x24, 0x7, 1, buf, 1);
432 i2c_write(0x24, 0x8, 1, buf, 1);
436 int arch_early_init_r(void)
442 static int board_video_init(void)
445 int anzdisp = ARRAY_SIZE(lcd_panels);
448 for (i = 0; i < anzdisp; i++) {
449 if (strncmp((const char *)factory_dat.disp_name,
451 strlen((const char *)factory_dat.disp_name)) == 0) {
452 printf("DISPLAY: %s\n", factory_dat.disp_name);
458 printf("%s: %s not found, using default %s\n", __func__,
459 factory_dat.disp_name, lcd_panels[i].name);
461 conf_disp_pll(24, 1);
462 da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
463 lcd_cfgs[display].bpp);
467 #endif /* ifdef CONFIG_VIDEO */
469 #ifdef CONFIG_BOARD_LATE_INIT
470 int board_late_init(void)
473 char tmp[2 * MAX_STRING_LENGTH + 2];
475 omap_nand_switch_ecc(1, 8);
477 if (factory_dat.asn[0] != 0)
478 sprintf(tmp, "%s_%s", factory_dat.asn,
479 factory_dat.comp_version);
481 strcpy(tmp, "QMX7.E38_4.0");
483 ret = env_set("boardid", tmp);
485 printf("error setting board id\n");
491 #include "../common/board.c"