1 // SPDX-License-Identifier: GPL-2.0+
3 * Board functions for TI AM335X based pxm2 board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * u-boot:/board/ti/am335x/board.c
10 * Board functions for TI AM335X based boards
12 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/omap.h>
26 #include <asm/arch/ddr_defs.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sys_proto.h>
31 #include "../../../drivers/video/da8xx-fb.h"
40 #include "../common/factoryset.h"
43 #include <bmp_layout.h>
45 #ifdef CONFIG_SPL_BUILD
46 static void board_init_ddr(void)
48 struct emif_regs pxm2_ddr3_emif_reg_data = {
49 .sdram_config = 0x41805332,
50 .sdram_tim1 = 0x666b3c9,
51 .sdram_tim2 = 0x243631ca,
53 .emif_ddr_phy_ctlr_1 = 0x100005,
58 struct ddr_data pxm2_ddr3_data = {
59 .datardsratio0 = 0x81204812,
61 .datafwsratio0 = 0x8020080,
62 .datawrsratio0 = 0x4010040,
65 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
74 const struct ctrl_ioregs ioregs = {
75 .cm0ioctl = DDR_IOCTRL_VAL,
76 .cm1ioctl = DDR_IOCTRL_VAL,
77 .cm2ioctl = DDR_IOCTRL_VAL,
78 .dt0ioctl = DDR_IOCTRL_VAL,
79 .dt1ioctl = DDR_IOCTRL_VAL,
82 config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
83 &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
87 * voltage switching for MPU frequency switching.
88 * @module = mpu - 0, core - 1
89 * @vddx_op_vol_sel = vdd voltage to set
95 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
98 unsigned int reg_offset;
101 reg_offset = PMIC_VDD1_OP_REG;
103 reg_offset = PMIC_VDD2_OP_REG;
106 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
109 buf[0] &= ~PMIC_OP_REG_CMD_MASK;
111 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
114 /* Configure VDDx OP Voltage */
115 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
118 buf[0] &= ~PMIC_OP_REG_SEL_MASK;
119 buf[0] |= vddx_op_vol_sel;
121 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
124 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
127 if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
133 #define OSC (V_OSCK/1000000)
135 const struct dpll_params dpll_mpu_pxm2 = {
136 720, OSC-1, 1, -1, -1, -1, -1};
138 void spl_siemens_board_init(void)
142 * pxm2 PMIC code. All boards currently want an MPU voltage
143 * of 1.2625V and CORE voltage of 1.1375V to operate at
146 if (i2c_probe(PMIC_CTRL_I2C_ADDR))
149 /* VDD1/2 voltage selection register access by control i/f */
150 if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
153 buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
155 if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
158 /* Frequency switching for OPP 120 */
159 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
160 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
161 printf("voltage update failed\n");
164 #endif /* if def CONFIG_SPL_BUILD */
166 int read_eeprom(void)
168 /* nothing ToDo here for this board */
173 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
174 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
175 static void cpsw_control(int enabled)
177 /* VTP can be added here */
182 static struct cpsw_slave_data cpsw_slaves[] = {
184 .slave_reg_ofs = 0x208,
185 .sliver_reg_ofs = 0xd80,
187 .phy_if = PHY_INTERFACE_MODE_RMII,
190 .slave_reg_ofs = 0x308,
191 .sliver_reg_ofs = 0xdc0,
193 .phy_if = PHY_INTERFACE_MODE_RMII,
197 static struct cpsw_platform_data cpsw_data = {
198 .mdio_base = CPSW_MDIO_BASE,
199 .cpsw_base = CPSW_BASE,
202 .cpdma_reg_ofs = 0x800,
204 .slave_data = cpsw_slaves,
205 .ale_reg_ofs = 0xd00,
207 .host_port_reg_ofs = 0x108,
208 .hw_stats_reg_ofs = 0x900,
209 .bd_ram_ofs = 0x2000,
210 .mac_control = (1 << 5),
211 .control = cpsw_control,
213 .version = CPSW_CTRL_VERSION_2,
215 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
217 #if defined(CONFIG_DRIVER_TI_CPSW) || \
218 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
219 int board_eth_init(bd_t *bis)
222 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
223 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
224 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
225 #ifdef CONFIG_FACTORYSET
227 if (!is_valid_ethaddr(factory_dat.mac))
228 printf("Error: no valid mac address\n");
230 eth_env_set_enetaddr("ethaddr", factory_dat.mac);
231 #endif /* #ifdef CONFIG_FACTORYSET */
233 /* Set rgmii mode and enable rmii clock to be sourced from chip */
234 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
236 rv = cpsw_register(&cpsw_data);
238 printf("Error %d registering CPSW switch\n", rv);
244 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
246 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
247 static struct da8xx_panel lcd_panels[] = {
248 /* AUO G156XW01 V1 */
250 .name = "AUO_G156XW01_V1",
262 /* AUO B101EVN06 V0 */
264 .name = "AUO_B101EVN06_V0",
277 * Settings from factoryset
281 .name = "factoryset",
295 static const struct display_panel disp_panel = {
302 static const struct lcd_ctrl_config lcd_cfg = {
312 .invert_line_clock = 1,
313 .invert_frm_clock = 1,
319 static int set_gpio(int gpio, int state)
321 gpio_request(gpio, "temp");
322 gpio_direction_output(gpio, state);
323 gpio_set_value(gpio, state);
328 static int enable_backlight(void)
330 set_gpio(BOARD_LCD_POWER, 1);
331 set_gpio(BOARD_BACK_LIGHT, 1);
332 set_gpio(BOARD_TOUCH_POWER, 1);
336 static int enable_pwm(void)
338 struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
339 struct pwmss_ecap_regs *ecap;
340 int ticks = PWM_TICKS;
343 ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
345 setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
346 /* TimeStam Counter register */
347 writel(0xdb9, &ecap->tsctr);
349 writel(ticks - 1, &ecap->cap3);
350 writel(ticks - 1, &ecap->cap1);
351 setbits_le16(&ecap->ecctl2,
352 (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
354 writel(duty, &ecap->cap2);
355 writel(duty, &ecap->cap4);
357 setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
361 static struct dpll_regs dpll_lcd_regs = {
362 .cm_clkmode_dpll = CM_WKUP + 0x98,
363 .cm_idlest_dpll = CM_WKUP + 0x48,
364 .cm_clksel_dpll = CM_WKUP + 0x54,
367 /* no console on this board */
368 int board_cfb_skip(void)
373 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
374 #define PLL_GET_N(v) (v & 0x7f)
376 static int get_clk(struct dpll_regs *dpll_regs)
382 val = readl(dpll_regs->cm_clksel_dpll);
385 f = (m * V_OSCK) / n;
392 return get_clk(&dpll_lcd_regs);
395 static int conf_disp_pll(int m, int n)
397 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
398 struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
399 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
401 u32 *const clk_domains[] = {
405 u32 *const clk_modules_explicit_en[] = {
407 &cmper->lcdcclkstctrl,
408 &cmper->epwmss0clkctrl,
411 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
412 writel(0x0, &cmdpll->clklcdcpixelclk);
414 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
419 static int board_video_init(void)
421 conf_disp_pll(24, 1);
422 if (factory_dat.pxm50)
423 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
425 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
434 #ifdef CONFIG_BOARD_LATE_INIT
435 int board_late_init(void)
439 omap_nand_switch_ecc(1, 8);
441 #ifdef CONFIG_FACTORYSET
442 if (factory_dat.asn[0] != 0) {
443 char tmp[2 * MAX_STRING_LENGTH + 2];
445 if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
446 factory_dat.pxm50 = 1;
448 factory_dat.pxm50 = 0;
449 sprintf(tmp, "%s_%s", factory_dat.asn,
450 factory_dat.comp_version);
451 ret = env_set("boardid", tmp);
453 printf("error setting board id\n");
455 factory_dat.pxm50 = 1;
456 ret = env_set("boardid", "PXM50_1.0");
458 printf("error setting board id\n");
460 debug("PXM50: %d\n", factory_dat.pxm50);
467 #include "../common/board.c"