3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* ------------------------------------------------------------------------- */
32 static long int dram_size (long int, long int *, long int);
33 static void puma_status (void);
34 static void puma_set_mode (int mode);
35 static int puma_init_done (void);
36 static void puma_load (ulong addr, ulong len);
38 /* ------------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
43 * 50 MHz SDRAM access using UPM A
45 const uint sdram_table[] = {
47 * Single Read. (Offset 0 in UPM RAM)
49 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
50 0x1ffddc47, /* last */
52 * SDRAM Initialization (offset 5 in UPM RAM)
54 * This is no UPM entry point. The following definition uses
55 * the remaining space to establish an initialization
56 * sequence, which is executed by a RUN command.
59 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
61 * Burst Read. (Offset 8 in UPM RAM)
63 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
64 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 * Single Write. (Offset 18 in UPM RAM)
71 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 * Burst Write. (Offset 20 in UPM RAM)
76 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
77 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 * Refresh (Offset 30 in UPM RAM)
84 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
85 0xfffffc84, 0xfffffc07, /* last */
86 _NOT_USED_, _NOT_USED_,
87 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
89 * Exception. (Offset 3c in UPM RAM)
91 0x7ffffc07, /* last */
92 _NOT_USED_, _NOT_USED_, _NOT_USED_,
95 /* ------------------------------------------------------------------------- */
98 * PUMA access using UPM B
100 const uint puma_table[] = {
102 * Single Read. (Offset 0 in UPM RAM)
104 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
109 _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 * Burst Read. (Offset 8 in UPM RAM)
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
116 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
118 * Single Write. (Offset 18 in UPM RAM)
120 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
122 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
124 * Burst Write. (Offset 20 in UPM RAM)
126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
128 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 * Refresh (Offset 30 in UPM RAM)
133 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
134 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
135 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 * Exception. (Offset 3c in UPM RAM)
139 0x7ffffc07, /* last */
140 _NOT_USED_, _NOT_USED_, _NOT_USED_,
143 /* ------------------------------------------------------------------------- */
147 * Check Board Identity:
151 int checkboard (void)
153 puts ("Board: Siemens PCU E\n");
157 /* ------------------------------------------------------------------------- */
159 long int initdram (int board_type)
161 volatile immap_t *immr = (immap_t *) CFG_IMMR;
162 volatile memctl8xx_t *memctl = &immr->im_memctl;
163 long int size_b0, reg;
167 * Configure UPMA for SDRAM
169 upmconfig (UPMA, (uint *) sdram_table,
170 sizeof (sdram_table) / sizeof (uint));
172 memctl->memc_mptpr = CFG_MPTPR;
174 /* burst length=4, burst type=sequential, CAS latency=2 */
175 memctl->memc_mar = 0x00000088;
178 * Map controller bank 2 to the SDRAM bank at preliminary address.
180 #if PCU_E_WITH_SWAPPED_CS /* XXX */
181 memctl->memc_or5 = CFG_OR5_PRELIM;
182 memctl->memc_br5 = CFG_BR5_PRELIM;
184 memctl->memc_or2 = CFG_OR2_PRELIM;
185 memctl->memc_br2 = CFG_BR2_PRELIM;
188 /* initialize memory address register */
189 memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
191 /* mode initialization (offset 5) */
192 #if PCU_E_WITH_SWAPPED_CS /* XXX */
193 udelay (200); /* 0x8000A105 */
194 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
196 udelay (200); /* 0x80004105 */
197 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
200 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
201 #if PCU_E_WITH_SWAPPED_CS /* XXX */
202 udelay (1); /* 0x8000A830 */
203 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
205 udelay (1); /* 0x80004830 */
206 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
209 #if PCU_E_WITH_SWAPPED_CS /* XXX */
210 udelay (1); /* 0x8000A106 */
211 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
213 udelay (1); /* 0x80004106 */
214 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
217 reg = memctl->memc_mamr;
218 reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
219 reg |= MAMR_TLFA_4X; /* ... to 4x */
220 reg |= MAMR_PTAE; /* enable refresh */
221 memctl->memc_mamr = reg;
225 /* Need at least 10 DRAM accesses to stabilize */
226 for (i = 0; i < 10; ++i) {
227 #if PCU_E_WITH_SWAPPED_CS /* XXX */
228 volatile unsigned long *addr =
229 (volatile unsigned long *) SDRAM_BASE5_PRELIM;
231 volatile unsigned long *addr =
232 (volatile unsigned long *) SDRAM_BASE2_PRELIM;
241 * Check Bank 0 Memory Size for re-configuration
243 #if PCU_E_WITH_SWAPPED_CS /* XXX */
244 size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
246 size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
249 memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
255 #if PCU_E_WITH_SWAPPED_CS /* XXX */
256 memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
257 memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
259 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
260 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
265 * Configure UPMB for PUMA
267 upmconfig (UPMB, (uint *) puma_table,
268 sizeof (puma_table) / sizeof (uint));
273 /* ------------------------------------------------------------------------- */
276 * Check memory range for valid RAM. A simple memory test determines
277 * the actually available RAM size between addresses `base' and
278 * `base + maxsize'. Some (not all) hardware errors are detected:
279 * - short between address lines
280 * - short between data lines
283 static long int dram_size (long int mamr_value, long int *base,
286 volatile immap_t *immr = (immap_t *) CFG_IMMR;
287 volatile memctl8xx_t *memctl = &immr->im_memctl;
289 memctl->memc_mamr = mamr_value;
291 return (get_ram_size (base, maxsize));
294 /* ------------------------------------------------------------------------- */
296 #if PCU_E_WITH_SWAPPED_CS /* XXX */
297 #define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
299 #define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
300 CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
303 #define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
305 void reset_phy (void)
307 immap_t *immr = (immap_t *) CFG_IMMR;
310 /* Configure all needed port pins for GPIO */
311 #if PCU_E_WITH_SWAPPED_CS /* XXX */
312 # ifdef CFG_ETH_MDDIS_VALUE
313 immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
315 immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
317 immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
318 immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
319 immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
321 immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
322 immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
324 value = immr->im_cpm.cp_pbdat;
326 /* Assert Powerdown and Reset signals */
327 value |= CFG_PB_ETH_POWERDOWN;
328 value &= ~(CFG_PB_ETH_RESET);
330 /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
331 #if !PCU_E_WITH_SWAPPED_CS
332 # ifdef CFG_ETH_MDDIS_VALUE
333 value |= CFG_PB_ETH_MDDIS;
335 value &= ~(CFG_PB_ETH_MDDIS);
338 #ifdef CFG_ETH_CFG1_VALUE
339 value |= CFG_PB_ETH_CFG1;
341 value &= ~(CFG_PB_ETH_CFG1);
343 #ifdef CFG_ETH_CFG2_VALUE
344 value |= CFG_PB_ETH_CFG2;
346 value &= ~(CFG_PB_ETH_CFG2);
348 #ifdef CFG_ETH_CFG3_VALUE
349 value |= CFG_PB_ETH_CFG3;
351 value &= ~(CFG_PB_ETH_CFG3);
354 /* Drive output signals to initial state */
355 immr->im_cpm.cp_pbdat = value;
356 immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
359 /* De-assert Ethernet Powerdown */
360 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
363 /* de-assert RESET signal of PHY */
364 immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
368 /*-----------------------------------------------------------------------
369 * Board Special Commands: access functions for "PUMA" FPGA
371 #if defined(CONFIG_CMD_BSP)
373 #define PUMA_READ_MODE 0
374 #define PUMA_LOAD_MODE 1
376 int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
381 case 2: /* PUMA reset */
382 if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
387 case 4: /* PUMA load addr len */
388 if (strcmp (argv[1], "load") != 0)
391 addr = simple_strtoul (argv[2], NULL, 16);
392 len = simple_strtoul (argv[3], NULL, 16);
394 printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
396 puma_load (addr, len);
402 printf ("Usage:\n%s\n", cmdtp->usage);
406 U_BOOT_CMD (puma, 4, 1, do_puma,
407 "puma - access PUMA FPGA\n",
408 "status - print PUMA status\n"
409 "puma load addr len - load PUMA configuration data\n");
413 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
415 static void puma_set_mode (int mode)
417 volatile immap_t *immr = (immap_t *) CFG_IMMR;
418 volatile memctl8xx_t *memctl = &immr->im_memctl;
420 /* disable PUMA in memory controller */
421 #if PCU_E_WITH_SWAPPED_CS /* XXX */
422 memctl->memc_br3 = 0;
424 memctl->memc_br4 = 0;
429 #if PCU_E_WITH_SWAPPED_CS /* XXX */
430 memctl->memc_or3 = PUMA_CONF_OR_READ;
431 memctl->memc_br3 = PUMA_CONF_BR_READ;
433 memctl->memc_or4 = PUMA_CONF_OR_READ;
434 memctl->memc_br4 = PUMA_CONF_BR_READ;
438 #if PCU_E_WITH_SWAPPED_CS /* XXX */
439 memctl->memc_or3 = PUMA_CONF_OR_LOAD;
440 memctl->memc_br3 = PUMA_CONF_BR_LOAD;
442 memctl->memc_or4 = PUMA_CONF_OR_READ;
443 memctl->memc_br4 = PUMA_CONF_BR_READ;
449 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
451 #define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
453 static void puma_load (ulong addr, ulong len)
455 volatile immap_t *immr = (immap_t *) CFG_IMMR;
456 volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
457 uchar *data = (uchar *) addr;
465 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
466 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
467 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
469 #if PCU_E_WITH_SWAPPED_CS /* XXX */
470 immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
471 immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
472 immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
473 immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
475 immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
476 immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
477 immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
478 immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
482 #if PCU_E_WITH_SWAPPED_CS /* XXX */
483 immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
485 immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
488 /* wait until INIT indicates completion of reset */
489 for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
491 if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
494 if (i == PUMA_INIT_TIMEOUT) {
495 printf ("*** PUMA init timeout ***\n");
499 puma_set_mode (PUMA_LOAD_MODE);
502 *fpga_addr = *data++;
504 puma_set_mode (PUMA_READ_MODE);
509 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
511 static void puma_status (void)
514 printf ("PUMA initialization is %scomplete\n",
515 puma_init_done ()? "" : "NOT ");
518 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
520 static int puma_init_done (void)
522 volatile immap_t *immr = (immap_t *) CFG_IMMR;
524 /* make sure pin is GPIO input */
525 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
526 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
527 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
529 return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
532 /* ------------------------------------------------------------------------- */
534 int misc_init_r (void)
541 if (puma_init_done ()) {
542 printf ("initialized\n");
546 if ((s = getenv ("puma_addr")) != NULL)
547 addr = simple_strtoul (s, NULL, 16);
549 if ((s = getenv ("puma_len")) != NULL)
550 len = simple_strtoul (s, NULL, 16);
552 if ((!addr) || (!len)) {
553 printf ("net list undefined\n");
557 printf ("loading... ");
559 puma_load (addr, len);
563 /* ------------------------------------------------------------------------- */