3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* ------------------------------------------------------------------------- */
32 static long int dram_size (long int, long int *, long int);
33 static void puma_status (void);
34 static void puma_set_mode (int mode);
35 static int puma_init_done (void);
36 static void puma_load (ulong addr, ulong len);
38 /* ------------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
43 * 50 MHz SDRAM access using UPM A
45 const uint sdram_table[] =
48 * Single Read. (Offset 0 in UPM RAM)
50 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
51 0x1ffddc47, /* last */
53 * SDRAM Initialization (offset 5 in UPM RAM)
55 * This is no UPM entry point. The following definition uses
56 * the remaining space to establish an initialization
57 * sequence, which is executed by a RUN command.
60 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
62 * Burst Read. (Offset 8 in UPM RAM)
64 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
65 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 * Single Write. (Offset 18 in UPM RAM)
72 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 * Burst Write. (Offset 20 in UPM RAM)
77 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
78 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 * Refresh (Offset 30 in UPM RAM)
85 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
86 0xfffffc84, 0xfffffc07, /* last */
87 _NOT_USED_, _NOT_USED_,
88 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 * Exception. (Offset 3c in UPM RAM)
92 0x7ffffc07, /* last */
93 _NOT_USED_, _NOT_USED_, _NOT_USED_,
96 /* ------------------------------------------------------------------------- */
99 * PUMA access using UPM B
101 const uint puma_table[] =
104 * Single Read. (Offset 0 in UPM RAM)
106 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 * Burst Read. (Offset 8 in UPM RAM)
115 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
116 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 * Single Write. (Offset 18 in UPM RAM)
122 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
124 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 * Burst Write. (Offset 20 in UPM RAM)
128 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
133 * Refresh (Offset 30 in UPM RAM)
135 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
136 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
139 * Exception. (Offset 3c in UPM RAM)
141 0x7ffffc07, /* last */
142 _NOT_USED_, _NOT_USED_, _NOT_USED_,
145 /* ------------------------------------------------------------------------- */
149 * Check Board Identity:
153 int checkboard (void)
155 puts ("Board: Siemens PCU E\n");
159 /* ------------------------------------------------------------------------- */
162 initdram (int board_type)
164 volatile immap_t *immr = (immap_t *)CFG_IMMR;
165 volatile memctl8xx_t *memctl = &immr->im_memctl;
166 long int size_b0, reg;
170 * Configure UPMA for SDRAM
172 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
174 memctl->memc_mptpr = CFG_MPTPR;
176 /* burst length=4, burst type=sequential, CAS latency=2 */
177 memctl->memc_mar = 0x00000088;
180 * Map controller bank 2 to the SDRAM bank at preliminary address.
182 #if PCU_E_WITH_SWAPPED_CS /* XXX */
183 memctl->memc_or5 = CFG_OR5_PRELIM;
184 memctl->memc_br5 = CFG_BR5_PRELIM;
186 memctl->memc_or2 = CFG_OR2_PRELIM;
187 memctl->memc_br2 = CFG_BR2_PRELIM;
190 /* initialize memory address register */
191 memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
193 /* mode initialization (offset 5) */
194 #if PCU_E_WITH_SWAPPED_CS /* XXX */
195 udelay(200); /* 0x8000A105 */
196 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
198 udelay(200); /* 0x80004105 */
199 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
202 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
203 #if PCU_E_WITH_SWAPPED_CS /* XXX */
204 udelay(1); /* 0x8000A830 */
205 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
207 udelay(1); /* 0x80004830 */
208 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
211 #if PCU_E_WITH_SWAPPED_CS /* XXX */
212 udelay(1); /* 0x8000A106 */
213 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
215 udelay(1); /* 0x80004106 */
216 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
219 reg = memctl->memc_mamr;
220 reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
221 reg |= MAMR_TLFA_4X; /* ... to 4x */
222 reg |= MAMR_PTAE; /* enable refresh */
223 memctl->memc_mamr = reg;
227 /* Need at least 10 DRAM accesses to stabilize */
228 for (i=0; i<10; ++i) {
229 #if PCU_E_WITH_SWAPPED_CS /* XXX */
230 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
232 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
241 * Check Bank 0 Memory Size for re-configuration
243 #if PCU_E_WITH_SWAPPED_CS /* XXX */
244 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
246 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
249 memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
255 #if PCU_E_WITH_SWAPPED_CS /* XXX */
256 memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
257 memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
259 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
260 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
265 * Configure UPMB for PUMA
267 upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
272 /* ------------------------------------------------------------------------- */
275 * Check memory range for valid RAM. A simple memory test determines
276 * the actually available RAM size between addresses `base' and
277 * `base + maxsize'. Some (not all) hardware errors are detected:
278 * - short between address lines
279 * - short between data lines
282 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
284 volatile immap_t *immr = (immap_t *)CFG_IMMR;
285 volatile memctl8xx_t *memctl = &immr->im_memctl;
286 volatile long int *addr;
288 ulong save[32]; /* to make test non-destructive */
291 memctl->memc_mamr = mamr_value;
293 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
294 addr = base + cnt; /* pointer arith! */
300 /* write 0 to base address */
305 /* check at base address */
306 if ((val = *addr) != 0) {
311 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
312 addr = base + cnt; /* pointer arith! */
318 return (cnt * sizeof(long));
324 /* ------------------------------------------------------------------------- */
326 #if PCU_E_WITH_SWAPPED_CS /* XXX */
327 #define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
329 #define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
330 CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
333 #define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
337 immap_t *immr = (immap_t *)CFG_IMMR;
340 /* Configure all needed port pins for GPIO */
341 #if PCU_E_WITH_SWAPPED_CS /* XXX */
342 # if CFG_ETH_MDDIS_VALUE
343 immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
345 immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
347 immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
348 immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
349 immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
351 immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
352 immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
354 value = immr->im_cpm.cp_pbdat;
356 /* Assert Powerdown and Reset signals */
357 value |= CFG_PB_ETH_POWERDOWN;
358 value &= ~(CFG_PB_ETH_RESET);
360 /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
361 #if !PCU_E_WITH_SWAPPED_CS
362 # if CFG_ETH_MDDIS_VALUE
363 value |= CFG_PB_ETH_MDDIS;
365 value &= ~(CFG_PB_ETH_MDDIS);
368 #if CFG_ETH_CFG1_VALUE
369 value |= CFG_PB_ETH_CFG1;
371 value &= ~(CFG_PB_ETH_CFG1);
373 #if CFG_ETH_CFG2_VALUE
374 value |= CFG_PB_ETH_CFG2;
376 value &= ~(CFG_PB_ETH_CFG2);
378 #if CFG_ETH_CFG3_VALUE
379 value |= CFG_PB_ETH_CFG3;
381 value &= ~(CFG_PB_ETH_CFG3);
384 /* Drive output signals to initial state */
385 immr->im_cpm.cp_pbdat = value;
386 immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
389 /* De-assert Ethernet Powerdown */
390 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
393 /* de-assert RESET signal of PHY */
394 immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
398 /*-----------------------------------------------------------------------
399 * Board Special Commands: access functions for "PUMA" FPGA
401 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
403 #define PUMA_READ_MODE 0
404 #define PUMA_LOAD_MODE 1
406 int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
411 case 2: /* PUMA reset */
412 if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
417 case 4: /* PUMA load addr len */
418 if (strcmp(argv[1],"load") != 0)
421 addr = simple_strtoul(argv[2], NULL, 16);
422 len = simple_strtoul(argv[3], NULL, 16);
424 printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
426 puma_load (addr, len);
432 printf ("Usage:\n%s\n", cmdtp->usage);
437 "puma - access PUMA FPGA\n",
438 "status - print PUMA status\n"
439 "puma load addr len - load PUMA configuration data\n"
442 #endif /* CFG_CMD_BSP */
444 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
446 static void puma_set_mode (int mode)
448 volatile immap_t *immr = (immap_t *)CFG_IMMR;
449 volatile memctl8xx_t *memctl = &immr->im_memctl;
451 /* disable PUMA in memory controller */
452 #if PCU_E_WITH_SWAPPED_CS /* XXX */
453 memctl->memc_br3 = 0;
455 memctl->memc_br4 = 0;
460 #if PCU_E_WITH_SWAPPED_CS /* XXX */
461 memctl->memc_or3 = PUMA_CONF_OR_READ;
462 memctl->memc_br3 = PUMA_CONF_BR_READ;
464 memctl->memc_or4 = PUMA_CONF_OR_READ;
465 memctl->memc_br4 = PUMA_CONF_BR_READ;
469 #if PCU_E_WITH_SWAPPED_CS /* XXX */
470 memctl->memc_or3 = PUMA_CONF_OR_LOAD;
471 memctl->memc_br3 = PUMA_CONF_BR_LOAD;
473 memctl->memc_or4 = PUMA_CONF_OR_READ;
474 memctl->memc_br4 = PUMA_CONF_BR_READ;
480 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
482 #define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
484 static void puma_load (ulong addr, ulong len)
486 volatile immap_t *immr = (immap_t *)CFG_IMMR;
487 volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
488 uchar *data = (uchar *)addr;
496 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
497 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
498 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
500 #if PCU_E_WITH_SWAPPED_CS /* XXX */
501 immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
502 immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
503 immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
504 immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
506 immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
507 immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
508 immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
509 immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
513 #if PCU_E_WITH_SWAPPED_CS /* XXX */
514 immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
516 immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
519 /* wait until INIT indicates completion of reset */
520 for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
522 if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
525 if (i == PUMA_INIT_TIMEOUT) {
526 printf ("*** PUMA init timeout ***\n");
530 puma_set_mode (PUMA_LOAD_MODE);
533 *fpga_addr = *data++;
535 puma_set_mode (PUMA_READ_MODE);
540 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
542 static void puma_status (void)
545 printf ("PUMA initialization is %scomplete\n",
546 puma_init_done() ? "" : "NOT ");
549 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
551 static int puma_init_done (void)
553 volatile immap_t *immr = (immap_t *)CFG_IMMR;
555 /* make sure pin is GPIO input */
556 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
557 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
558 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
560 return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
563 /* ------------------------------------------------------------------------- */
565 int misc_init_r (void)
572 if (puma_init_done()) {
573 printf ("initialized\n");
577 if ((s = getenv("puma_addr")) != NULL)
578 addr = simple_strtoul(s, NULL, 16);
580 if ((s = getenv("puma_len")) != NULL)
581 len = simple_strtoul(s, NULL, 16);
583 if ((!addr) || (!len)) {
584 printf ("net list undefined\n");
588 printf ("loading... ");
590 puma_load (addr, len);
594 /* ------------------------------------------------------------------------- */