2 * Board functions for TI AM335X based dxr2 board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * Board functions for TI AM335X based boards
9 * u-boot:/board/ti/am335x/board.c
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #ifdef CONFIG_SPL_BUILD
40 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
42 const struct ddr3_data ddr3_default = {
43 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
44 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
48 static void set_default_ddr3_timings(void)
50 printf("Set default DDR3 settings\n");
51 settings.ddr3 = ddr3_default;
54 static void print_ddr3_timings(void)
56 printf("\n\nDDR3 Timing parameters:\n");
57 printf("Diff Eeprom Default\n");
60 PRINTARGS(ddr3_sratio);
63 PRINTARGS(dt0rdsratio0);
64 PRINTARGS(dt0wdsratio0);
65 PRINTARGS(dt0fwsratio0);
66 PRINTARGS(dt0wrsratio0);
68 PRINTARGS(sdram_tim1);
69 PRINTARGS(sdram_tim2);
70 PRINTARGS(sdram_tim3);
72 PRINTARGS(emif_ddr_phy_ctlr_1);
74 PRINTARGS(sdram_config);
78 static void print_chip_data(void)
81 printf("Device: '%s'\n", settings.chip.sdevname);
82 printf("HW version: '%s'\n", settings.chip.shwver);
84 #endif /* CONFIG_SPL_BUILD */
87 * Read header information from EEPROM into global structure.
89 static int read_eeprom(void)
91 /* Check if baseboard eeprom is available */
92 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
93 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
97 #ifdef CONFIG_SPL_BUILD
98 /* Read Siemens eeprom data (DDR3) */
99 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
100 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
101 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
102 set_default_ddr3_timings();
104 /* Read Siemens eeprom data (CHIP) */
105 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
106 (uchar *)&settings.chip, sizeof(settings.chip)))
107 printf("Could not read chip settings\n");
109 if (ddr3_default.magic == settings.ddr3.magic &&
110 ddr3_default.version == settings.ddr3.version) {
111 printf("Using DDR3 settings from EEPROM\n");
113 if (ddr3_default.magic != settings.ddr3.magic)
114 printf("Error: No valid DDR3 data in eeprom.\n");
115 if (ddr3_default.version != settings.ddr3.version)
116 printf("Error: DDR3 data version does not match.\n");
118 printf("Using default settings\n");
119 set_default_ddr3_timings();
122 if (MAGIC_CHIP == settings.chip.magic) {
123 printf("Valid chip data in eeprom\n");
126 printf("Error: No chip data in eeprom\n");
129 print_ddr3_timings();
134 #ifdef CONFIG_SPL_BUILD
135 static void board_init_ddr(void)
137 struct emif_regs dxr2_ddr3_emif_reg_data = {
138 .zq_config = 0x50074BE4,
141 struct ddr_data dxr2_ddr3_data = {
142 .datadldiff0 = PHY_DLL_LOCK_DIFF,
145 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
150 /* pass values from eeprom */
151 dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
152 dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
153 dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
154 dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
155 settings.ddr3.emif_ddr_phy_ctlr_1;
156 dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
157 dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
159 dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
160 dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
161 dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
162 dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
164 dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
165 dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
166 dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
167 dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
168 dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
169 dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
171 config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
172 &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
175 static void spl_siemens_board_init(void)
179 #endif /* if def CONFIG_SPL_BUILD */
181 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
182 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
183 static void cpsw_control(int enabled)
185 /* VTP can be added here */
190 static struct cpsw_slave_data cpsw_slaves[] = {
192 .slave_reg_ofs = 0x208,
193 .sliver_reg_ofs = 0xd80,
195 .phy_if = PHY_INTERFACE_MODE_MII,
199 static struct cpsw_platform_data cpsw_data = {
200 .mdio_base = CPSW_MDIO_BASE,
201 .cpsw_base = CPSW_BASE,
204 .cpdma_reg_ofs = 0x800,
206 .slave_data = cpsw_slaves,
207 .ale_reg_ofs = 0xd00,
209 .host_port_reg_ofs = 0x108,
210 .hw_stats_reg_ofs = 0x900,
211 .bd_ram_ofs = 0x2000,
212 .mac_control = (1 << 5),
213 .control = cpsw_control,
215 .version = CPSW_CTRL_VERSION_2,
218 #if defined(CONFIG_DRIVER_TI_CPSW) || \
219 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
220 int board_eth_init(bd_t *bis)
222 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
228 /* Set rgmii mode and enable rmii clock to be sourced from chip */
229 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
231 rv = cpsw_register(&cpsw_data);
233 printf("Error %d registering CPSW switch\n", rv);
238 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
239 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
241 #include "../common/board.c"