2 * Board functions for TI AM335X based draco board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * Board functions for TI AM335X based boards
9 * u-boot:/board/ti/am335x/board.c
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #ifdef CONFIG_SPL_BUILD
40 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
42 #if DDR_PLL_FREQ == 303
43 /* Default@303MHz-i0 */
44 const struct ddr3_data ddr3_default = {
45 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
46 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
47 0x0000093B, 0x0000014A,
48 "default name @303MHz \0",
51 #elif DDR_PLL_FREQ == 400
52 /* Default@400MHz-i0 */
53 const struct ddr3_data ddr3_default = {
54 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
55 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
56 0x00000618, 0x0000014A,
57 "default name @400MHz \0",
62 static void set_default_ddr3_timings(void)
64 printf("Set default DDR3 settings\n");
65 settings.ddr3 = ddr3_default;
68 static void print_ddr3_timings(void)
71 printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
72 printf("device:\t\t%s\n", settings.ddr3.manu_name);
73 printf("marking:\t%s\n", settings.ddr3.manu_marking);
74 printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
78 PRINTARGS(ddr3_sratio);
81 PRINTARGS(dt0rdsratio0);
82 PRINTARGS(dt0wdsratio0);
83 PRINTARGS(dt0fwsratio0);
84 PRINTARGS(dt0wrsratio0);
86 PRINTARGS(sdram_tim1);
87 PRINTARGS(sdram_tim2);
88 PRINTARGS(sdram_tim3);
90 PRINTARGS(emif_ddr_phy_ctlr_1);
92 PRINTARGS(sdram_config);
97 static void print_chip_data(void)
99 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
100 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
101 printf("\nCPU BOARD\n");
102 printf("device: \t'%s'\n", settings.chip.sdevname);
103 printf("hw version: \t'%s'\n", settings.chip.shwver);
104 printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
106 #endif /* CONFIG_SPL_BUILD */
109 * Read header information from EEPROM into global structure.
111 static int read_eeprom(void)
113 /* Check if baseboard eeprom is available */
114 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
115 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
119 #ifdef CONFIG_SPL_BUILD
120 /* Read Siemens eeprom data (DDR3) */
121 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
122 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
123 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
124 set_default_ddr3_timings();
126 /* Read Siemens eeprom data (CHIP) */
127 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
128 (uchar *)&settings.chip, sizeof(settings.chip)))
129 printf("Could not read chip settings\n");
131 if (ddr3_default.magic == settings.ddr3.magic &&
132 ddr3_default.version == settings.ddr3.version) {
133 printf("Using DDR3 settings from EEPROM\n");
135 if (ddr3_default.magic != settings.ddr3.magic)
136 printf("Warning: No valid DDR3 data in eeprom.\n");
137 if (ddr3_default.version != settings.ddr3.version)
138 printf("Warning: DDR3 data version does not match.\n");
140 printf("Using default settings\n");
141 set_default_ddr3_timings();
144 if (MAGIC_CHIP == settings.chip.magic)
147 printf("Warning: No chip data in eeprom\n");
149 print_ddr3_timings();
154 #ifdef CONFIG_SPL_BUILD
155 static void board_init_ddr(void)
157 struct emif_regs draco_ddr3_emif_reg_data = {
158 .zq_config = 0x50074BE4,
161 struct ddr_data draco_ddr3_data = {
164 struct cmd_control draco_ddr3_cmd_ctrl_data = {
167 struct ctrl_ioregs draco_ddr3_ioregs = {
170 /* pass values from eeprom */
171 draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
172 draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
173 draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
174 draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
175 settings.ddr3.emif_ddr_phy_ctlr_1;
176 draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
177 draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
179 draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
180 draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
181 draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
182 draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
184 draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
185 draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
186 draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
187 draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
188 draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
189 draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
191 draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
192 draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
193 draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
194 draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
195 draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
197 config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
198 &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
200 /* For Samsung 2Gbit RAM we need this delay otherwise config fails after
206 static void spl_siemens_board_init(void)
210 #endif /* if def CONFIG_SPL_BUILD */
212 #ifdef CONFIG_BOARD_LATE_INIT
213 int board_late_init(void)
215 omap_nand_switch_ecc(1, 8);
216 #ifdef CONFIG_FACTORYSET
217 /* Set ASN in environment*/
218 if (factory_dat.asn[0] != 0) {
219 setenv("dtb_name", (char *)factory_dat.asn);
221 /* dtb suffix gets added in load script */
222 setenv("dtb_name", "am335x-draco");
225 setenv("dtb_name", "am335x-draco");
232 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
233 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
234 static void cpsw_control(int enabled)
236 /* VTP can be added here */
241 static struct cpsw_slave_data cpsw_slaves[] = {
243 .slave_reg_ofs = 0x208,
244 .sliver_reg_ofs = 0xd80,
246 .phy_if = PHY_INTERFACE_MODE_MII,
250 static struct cpsw_platform_data cpsw_data = {
251 .mdio_base = CPSW_MDIO_BASE,
252 .cpsw_base = CPSW_BASE,
255 .cpdma_reg_ofs = 0x800,
257 .slave_data = cpsw_slaves,
258 .ale_reg_ofs = 0xd00,
260 .host_port_reg_ofs = 0x108,
261 .hw_stats_reg_ofs = 0x900,
262 .bd_ram_ofs = 0x2000,
263 .mac_control = (1 << 5),
264 .control = cpsw_control,
266 .version = CPSW_CTRL_VERSION_2,
269 #if defined(CONFIG_DRIVER_TI_CPSW) || \
270 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
271 int board_eth_init(bd_t *bis)
273 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
279 /* Set rgmii mode and enable rmii clock to be sourced from chip */
280 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
282 rv = cpsw_register(&cpsw_data);
284 printf("Error %d registering CPSW switch\n", rv);
290 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
293 /* Reset SMSC LAN9303 switch for default configuration */
294 gpio_request(GPIO_LAN9303_NRST, "nRST");
295 gpio_direction_output(GPIO_LAN9303_NRST, 0);
296 /* assert active low reset for 200us */
298 gpio_set_value(GPIO_LAN9303_NRST, 1);
304 switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
305 "Reset LAN9303 switch via its reset pin",
308 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
309 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
311 #include "../common/board.c"