1 /*------------------------------------------------------------------------------+
3 * This souce code has been made available to you by EuroDesign
4 * (www.eurodsn.de). It's based on the original IBM source code, so
7 * This source code has been made available to you by IBM on an AS-IS
8 * basis. Anyone receiving this source is licensed under IBM
9 * copyrights to use it in any way he or she deems fit, including
10 * copying it, modifying it, compiling it, and redistributing it either
11 * with or without modifications. No license under IBM patents or
12 * patent applications is to be implied by the copyright license.
14 * Any user of this software should understand that IBM cannot provide
15 * technical support for this software and will not be responsible for
16 * any consequences resulting from the use of this software.
18 * Any person who transfers this source code or any derivative work
19 * must include the IBM copyright notice, this paragraph, and the
20 * preceding two paragraphs in the transferred software.
22 * COPYRIGHT I B M CORPORATION 1995
23 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
24 *------------------------------------------------------------------------------- */
29 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
31 #include <ppc_asm.tmpl>
34 #include <asm/cache.h>
38 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
40 * IMPORTANT: For pass1 this code must run from cache since you can not
41 * reliably change a peripheral banks timing register (pbxap) while running
42 * code from that bank. For ex., since we are running from ROM on bank 0, we
43 * can NOT execute the code that modifies bank 0 timings from ROM, so
44 * we run it from cache.
49 * Bank 3 - Second Flash
50 * Bank 4 - USB controller
52 .globl ext_bus_cntlr_init
55 * We need the current boot up configuration to set correct
56 * timings into internal flash and external flash
58 mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
59 0 0 -> 8 bit external ROM
60 0 1 -> 16 bit internal ROM */
62 srw r24,r24,r4 /* shift right r24 two positions */
65 * All calculations are based on 33MHz EBC clock.
67 * First, create a "very slow" timing (~250ns) with burst mode enabled
68 * This is need for the external flash access
71 ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
73 * Second, create a fast timing:
74 * 90ns first cycle - 3 clock access
75 * and 90ns burst cycle, plus 1 clock after the last access
76 * This is used for the internal access
79 ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
81 * We can't change settings on CS# if we currently use them.
82 * -> load a few instructions into cache and run this code from cache
84 mflr r4 /* save link register */
87 mflr r3 /* get address of ..getAddr */
88 mtlr r4 /* restore link register */
89 addi r4,0,14 /* set ctr to 10; used to prefetch */
90 mtctr r4 /* 10 cache lines to fit this function
91 in cache (gives us 8x10=80 instructions) */
93 icbt r0,r3 /* prefetch cache line for addr in r3 */
94 addi r3,r3,32 /* move to next cache line */
95 bdnz ..ebcloop /* continue for 10 cache lines */
97 * Delay to ensure all accesses to ROM are complete before changing
98 * bank 0 timings. 200usec should be enough.
99 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
102 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
105 bdnz ..spinlp /* spin loop */
107 /*-----------------------------------------------------------------------
108 * Memory Bank 0 (BOOT-ROM) initialization
109 * 0xFFEF00000....0xFFFFFFF
110 * We only have to change the timing. Mapping is ok by boot-strapping
111 *----------------------------------------------------------------------- */
113 li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */
116 mr r4,r26 /* assume internal fast flash is boot flash */
117 cmpwi r24,0x2000 /* assumption true? ... */
119 mr r4,r25 /* ...no, use the slow variant */
120 mr r25,r26 /* use this for the other flash */
122 mtdcr ebccfgd,r4 /* change timing now */
124 li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */
128 ori r3,r3,0x8000 /* allow reads and writes */
132 /*-----------------------------------------------------------------------
133 * Memory Bank 3 (Second-Flash) initialization
134 * 0xF0000000...0xF01FFFFF -> 2MB
135 *----------------------------------------------------------------------- */
137 li r4,pb3ap /* Peripheral Bank 1 Access Parameter */
139 mtdcr ebccfgd,r2 /* change timing */
141 li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */
147 * Consider boot configuration
149 xori r24,r24,0x2000 /* invert current bus width */
153 /*-----------------------------------------------------------------------
154 * Memory Bank 1 (NAND-Flash) initialization
155 * 0x77D00000...0x77DFFFFF -> 1MB
156 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
157 * - the setup time is 0ns
158 * - the hold time is 15ns
166 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
167 *----------------------------------------------------------------------- */
169 li r4,pb1ap /* Peripheral Bank 1 Access Parameter */
176 li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */
184 /* USB init (without acceleration) */
185 #ifndef CONFIG_ISP1161_PRESENT
186 li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
193 /*-----------------------------------------------------------------------
194 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
195 * 0x78000000...0x7BFFFFFF -> 64 MB
196 * Wir arbeiten bei 33 MHz -> 30ns
197 *-----------------------------------------------------------------------
199 A7 (ppc notation) or A24 (standard notation) decides about
201 A7/A24=0 -> memory cycle
202 A7/ /A24=1 -> I/O cycle
204 li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
207 We emulate an ISA access
210 2. wait 0 EBC clocks -> CSN=0
212 4. wait 0 EBC clock -> OEN/WBN=0
214 6. wait 4 clocks (ca. 90ns) and for Ready signal
215 7. hold for 4 clocks -> TH=4
219 /* faster access to isa-bus */
228 #ifdef IDE_USES_ISA_EMULATION
229 li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */
234 li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */
237 li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */
241 li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */
248 * the other areas are only 1MiB in size
253 li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
259 li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
265 #ifndef CONFIG_ISP1161_PRESENT
266 li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */
272 #ifdef IDE_USES_ISA_EMULATION
273 li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */
280 /*-----------------------------------------------------------------------
281 * Memory bank 4: USB controller Philips ISP6111
282 * 0x77C00000 ... 0x77CFFFFF
284 * The chip is connected to:
290 * - command to first data: 300ns. Software must ensure this timing!
291 * - Write pulse: 26ns
293 * - read cycle time: 150ns
294 * - write cycle time: 140ns
296 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
299 * |---- 420ns ---|---- 420ns ---| cycle
300 * CS ############:###____#######:###____#######
301 * OE ############:####___#######:####___#######
302 * WE ############:####__########:####__########
304 * ----> 2 clocks RD/WR pulses: 60ns
305 * ----> CSN: 3 clock, 90ns
306 * ----> OEN: 1 clocks (read cycle)
307 * ----> WBN: 1 clocks (write cycle)
308 * ----> WBE: 2 clocks
309 * ----> TH: 7 clock, 210ns
310 * ----> TWT: 7 clocks
311 *----------------------------------------------------------------------- */
313 #ifdef CONFIG_ISP1161_PRESENT
315 li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
322 li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */
331 #ifndef IDE_USES_ISA_EMULATION
333 /*-----------------------------------------------------------------------
334 * Memory Bank 5 used for IDE access
336 * Timings for IDE Interface
338 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
339 * 70 165 30 PIO-Mode 0, [ns]
340 * 3 6 1 [Cycles] ----> AP=0x040C0200
341 * 50 125 20 PIO-Mode 1, [ns]
342 * 2 5 1 [Cycles] ----> AP=0x03080200
343 * 30 100 15 PIO-Mode 2, [ns]
344 * 1 4 1 [Cycles] ----> AP=0x02040200
345 * 30 80 10 PIO-Mode 3, [ns]
346 * 1 3 1 [Cycles] ----> AP=0x01840200
347 * 25 70 10 PIO-Mode 4, [ns]
348 * 1 3 1 [Cycles] ----> AP=0x01840200
350 *----------------------------------------------------------------------- */
358 li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */
366 * External Peripheral Control Register
380 stb r3,0(r4) /* 01 -> external bus controller is initialized */
381 nop /* pass2 DCR errata #8 */