2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman joe.hamman@embeddedspecialties.com
6 * Copyright 2004 Freescale Semiconductor.
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <ppc_asm.tmpl>
31 #include <asm/cache.h>
37 * LAW(Local Access Window) configuration:
39 * 0x0000_0000 0x0fff_ffff DDR1 256M
40 * 0x1000_0000 0x1fff_ffff DDR2 256M
41 * 0xe000_0000 0xffff_ffff LBC 512M
44 * CCSRBAR doesn't need a configured Local Access Window.
45 * If flash is 8M at default position (last 8M), no LAW needed.
49 # #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
50 # #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
53 # #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
54 # #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
57 # #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
58 # #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
61 * LAW (Local Access Window) configuration:
63 * 0x0000_0000 DDR 256M
64 * 0x1000_0000 DDR2 256M
65 * 0x8000_0000 PCI1 MEM 512M
66 * 0xa000_0000 PCI2 MEM 512M
67 * 0xc000_0000 RapidIO 512M
68 * 0xe200_0000 PCI1 IO 16M
69 * 0xe300_0000 PCI2 IO 16M
70 * 0xf800_0000 CCSRBAR 2M
71 * 0xfe00_0000 FLASH (boot bank) 32M
75 #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
76 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
78 #define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
79 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
81 #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
82 #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
84 #define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
85 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
87 #define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
88 #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
90 #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
91 #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
93 #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
94 #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
96 #define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
97 #define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
99 #define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
100 #define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
102 .section .bootpg, "ax"
106 ori r7,r7,CFG_CCSRBAR@l
111 /* Skip LAWAR0, start at LAWAR1 */
120 /* LAWBAR2, LAWAR2 */
129 /* LAWBAR3, LAWAR3 */
138 /* LAWBAR4, LAWAR4 */
147 /* LAWBAR5, LAWAR5 */
156 /* LAWBAR6, LAWAR6 */
165 /* LAWBAR7, LAWAR7 */
174 /* LAWBAR8, LAWAR8 */
183 /* LAWBAR9, LAWAR9 */