2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
5 * Copyright 2004, 2007 Freescale Semiconductor.
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/immap_fsl_pci.h>
36 #include <fdt_support.h>
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
42 DECLARE_GLOBAL_DATA_PTR;
44 extern long int spd_sdram(void);
46 void local_bus_init(void);
47 void sdram_init(void);
48 long int fixed_sdram (void);
50 int board_early_init_f (void)
57 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
58 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
59 volatile u_char *rev= (void *)CFG_BD_REV;
61 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
65 * Initialize local bus.
70 * Fix CPU2 errata: A core hang possible while executing a
71 * msync instruction and a snoopable transaction from an I/O
72 * master tagged to make quick forward progress is present.
74 ecm->eebpcr |= (1 << 16);
77 * Hack TSEC 3 and 4 IO voltages.
79 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
81 ecm->eedr = 0xffffffff; /* clear ecm errors */
82 ecm->eeer = 0xffffffff; /* enable ecm errors */
87 initdram(int board_type)
91 puts("Initializing\n");
93 #if defined(CONFIG_DDR_DLL)
96 * Work around to stabilize DDR DLL MSYNC_IN.
97 * Errata DDR9 seems to have been fixed.
98 * This is now the workaround for Errata DDR11:
99 * Override DLL = 1, Course Adj = 1, Tap Select = 0
102 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
104 gur->ddrdllcr = 0x81000000;
105 asm("sync;isync;msync");
110 #if defined(CONFIG_SPD_EEPROM)
111 dram_size = spd_sdram ();
113 dram_size = fixed_sdram ();
116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
118 * Initialize and enable DDR ECC.
120 ddr_enable_ecc(dram_size);
123 * SDRAM Initialization
132 * Initialize Local Bus
137 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
138 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
144 get_sys_info(&sysinfo);
145 clkdiv = (lbc->lcrr & 0x0f) * 2;
146 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
148 gur->lbiuiplldcr1 = 0x00078080;
150 gur->lbiuiplldcr0 = 0x7c0f1bf0;
151 } else if (clkdiv == 8) {
152 gur->lbiuiplldcr0 = 0x6c0f1bf0;
153 } else if (clkdiv == 4) {
154 gur->lbiuiplldcr0 = 0x5c0f1bf0;
157 lbc->lcrr |= 0x00030000;
159 asm("sync;isync;msync");
161 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
162 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
166 * Initialize SDRAM memory on the Local Bus.
171 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
174 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
175 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
180 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
183 * Setup SDRAM Base and Option Registers
185 lbc->or3 = CFG_OR3_PRELIM;
188 lbc->br3 = CFG_BR3_PRELIM;
191 lbc->lbcr = CFG_LBC_LBCR;
195 lbc->lsrt = CFG_LBC_LSRT;
196 lbc->mrtpr = CFG_LBC_MRTPR;
200 * MPC8548 uses "new" 15-16 style addressing.
202 lsdmr_common = CFG_LBC_LSDMR_COMMON;
203 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
206 * Issue PRECHARGE ALL command.
208 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
211 ppcDcbf((unsigned long) sdram_addr);
215 * Issue 8 AUTO REFRESH commands.
217 for (idx = 0; idx < 8; idx++) {
218 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
221 ppcDcbf((unsigned long) sdram_addr);
226 * Issue 8 MODE-set command.
228 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
231 ppcDcbf((unsigned long) sdram_addr);
235 * Issue NORMAL OP command.
237 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
240 ppcDcbf((unsigned long) sdram_addr);
241 udelay(200); /* Overkill. Must wait > 200 bus cycles */
243 #endif /* enable SDRAM init */
246 #if defined(CFG_DRAM_TEST)
250 uint *pstart = (uint *) CFG_MEMTEST_START;
251 uint *pend = (uint *) CFG_MEMTEST_END;
254 printf("Testing DRAM from 0x%08x to 0x%08x\n",
258 printf("DRAM test phase 1:\n");
259 for (p = pstart; p < pend; p++)
262 for (p = pstart; p < pend; p++) {
263 if (*p != 0xaaaaaaaa) {
264 printf ("DRAM test fails at: %08x\n", (uint) p);
269 printf("DRAM test phase 2:\n");
270 for (p = pstart; p < pend; p++)
273 for (p = pstart; p < pend; p++) {
274 if (*p != 0x55555555) {
275 printf ("DRAM test fails at: %08x\n", (uint) p);
280 printf("DRAM test passed.\n");
285 #if !defined(CONFIG_SPD_EEPROM)
286 /*************************************************************************
287 * fixed_sdram init -- doesn't use serial presence detect.
288 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
289 ************************************************************************/
290 long int fixed_sdram (void)
292 #define CFG_DDR_CONTROL 0xc300c000
294 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
296 ddr->cs0_bnds = 0x0000007f;
297 ddr->cs1_bnds = 0x008000ff;
298 ddr->cs2_bnds = 0x00000000;
299 ddr->cs3_bnds = 0x00000000;
300 ddr->cs0_config = 0x80010101;
301 ddr->cs1_config = 0x80010101;
302 ddr->cs2_config = 0x00000000;
303 ddr->cs3_config = 0x00000000;
304 ddr->ext_refrec = 0x00000000;
305 ddr->timing_cfg_0 = 0x00220802;
306 ddr->timing_cfg_1 = 0x38377322;
307 ddr->timing_cfg_2 = 0x0fa044C7;
308 ddr->sdram_cfg = 0x4300C000;
309 ddr->sdram_cfg_2 = 0x24401000;
310 ddr->sdram_mode = 0x23C00542;
311 ddr->sdram_mode_2 = 0x00000000;
312 ddr->sdram_interval = 0x05080100;
313 ddr->sdram_md_cntl = 0x00000000;
314 ddr->sdram_data_init = 0x00000000;
315 ddr->sdram_clk_cntl = 0x03800000;
316 asm("sync;isync;msync");
319 #if defined (CONFIG_DDR_ECC)
320 /* Enable ECC checking */
321 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
323 ddr->sdram_cfg = CFG_DDR_CONTROL;
326 return CFG_SDRAM_SIZE * 1024 * 1024;
330 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
331 /* For some reason the Tundra PCI bridge shows up on itself as a
332 * different device. Work around that by refusing to configure it.
334 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
336 static struct pci_config_table pci_sbc8548_config_table[] = {
337 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
338 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
339 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
340 mpc85xx_config_via_usbide, {0,0,0}},
341 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
342 mpc85xx_config_via_usb, {0,0,0}},
343 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
344 mpc85xx_config_via_usb2, {0,0,0}},
345 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
346 mpc85xx_config_via_power, {0,0,0}},
347 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
348 mpc85xx_config_via_ac97, {0,0,0}},
352 static struct pci_controller pci1_hose = {
353 config_table: pci_sbc8548_config_table};
354 #endif /* CONFIG_PCI */
357 static struct pci_controller pci2_hose;
358 #endif /* CONFIG_PCI2 */
361 static struct pci_controller pcie1_hose;
362 #endif /* CONFIG_PCIE1 */
364 int first_free_busno=0;
369 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
373 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
374 extern void fsl_pci_init(struct pci_controller *hose);
375 struct pci_controller *hose = &pci1_hose;
376 struct pci_config_table *table;
378 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
379 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
380 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
382 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
384 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
386 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
387 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
389 (pci_speed == 33333000) ? "33" :
390 (pci_speed == 66666000) ? "66" : "unknown",
391 pci_clk_sel ? "sync" : "async",
392 pci_agent ? "agent" : "host",
393 pci_arb ? "arbiter" : "external-arbiter"
398 pci_set_region(hose->regions + 0,
402 PCI_REGION_MEM | PCI_REGION_MEMORY);
405 /* outbound memory */
406 pci_set_region(hose->regions + 1,
413 pci_set_region(hose->regions + 2,
418 hose->region_count = 3;
420 /* relocate config table pointers */
421 hose->config_table = \
422 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
423 for (table = hose->config_table; table && table->vendor; table++)
424 table->config_device += gd->reloc_off;
426 hose->first_busno=first_free_busno;
427 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
430 first_free_busno=hose->last_busno+1;
431 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
432 #ifdef CONFIG_PCIX_CHECK
433 if (!(gur->pordevsr & PORDEVSR_PCI)) {
435 if (CONFIG_SYS_CLK_FREQ < 66000000)
436 printf("PCI-X will only work at 66 MHz\n");
438 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
439 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
440 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
444 printf (" PCI: disabled\n");
448 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
453 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
454 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
456 printf (" PCI2: 32 bit, 66 MHz, %s\n",
457 pci2_clk_sel ? "sync" : "async");
459 printf (" PCI2: disabled\n");
463 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
464 #endif /* CONFIG_PCI2 */
468 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
469 extern void fsl_pci_init(struct pci_controller *hose);
470 struct pci_controller *hose = &pcie1_hose;
471 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
473 int pcie_configured = io_sel >= 1;
475 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
476 printf ("\n PCIE connected to slot as %s (base address %x)",
477 pcie_ep ? "End Point" : "Root Complex",
480 if (pci->pme_msg_det) {
481 pci->pme_msg_det = 0xffffffff;
482 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
487 pci_set_region(hose->regions + 0,
491 PCI_REGION_MEM | PCI_REGION_MEMORY);
493 /* outbound memory */
494 pci_set_region(hose->regions + 1,
501 pci_set_region(hose->regions + 2,
507 hose->region_count = 3;
509 hose->first_busno=first_free_busno;
510 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
513 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
515 first_free_busno=hose->last_busno+1;
518 printf (" PCIE: disabled\n");
522 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
527 int last_stage_init(void)
532 #if defined(CONFIG_OF_BOARD_SETUP)
534 ft_pci_setup(void *blob, bd_t *bd)
538 node = fdt_path_offset(blob, "/aliases");
543 path = fdt_getprop(blob, node, "pci0", NULL);
545 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
546 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
551 path = fdt_getprop(blob, node, "pci1", NULL);
553 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
554 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
561 #if defined(CONFIG_OF_BOARD_SETUP)
563 ft_board_setup(void *blob, bd_t *bd)
565 ft_cpu_setup(blob, bd);
567 ft_pci_setup(blob, bd);