2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
40 #include <fdt_support.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 void local_bus_init(void);
45 void sdram_init(void);
46 long int fixed_sdram (void);
48 int board_early_init_f (void)
55 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
62 * Initialize local bus.
66 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
67 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
72 initdram(int board_type)
76 puts("Initializing\n");
78 #if defined(CONFIG_DDR_DLL)
81 * Work around to stabilize DDR DLL MSYNC_IN.
82 * Errata DDR9 seems to have been fixed.
83 * This is now the workaround for Errata DDR11:
84 * Override DLL = 1, Course Adj = 1, Tap Select = 0
87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
89 out_be32(&gur->ddrdllcr, 0x81000000);
90 asm("sync;isync;msync");
95 #if defined(CONFIG_SPD_EEPROM)
96 dram_size = fsl_ddr_sdram();
97 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
98 dram_size *= 0x100000;
100 dram_size = fixed_sdram ();
104 * SDRAM Initialization
113 * Initialize Local Bus
118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
125 get_sys_info(&sysinfo);
126 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
129 out_be32(&gur->lbiuiplldcr1, 0x00078080);
131 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
132 } else if (clkdiv == 8) {
133 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
134 } else if (clkdiv == 4) {
135 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
138 setbits_be32(&lbc->lcrr, 0x00030000);
140 asm("sync;isync;msync");
142 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
143 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
147 * Initialize SDRAM memory on the Local Bus.
152 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
155 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
164 * Setup SDRAM Base and Option Registers
166 out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
169 out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
172 out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
175 out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
178 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
182 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
183 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
187 * MPC8548 uses "new" 15-16 style addressing.
189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
190 lsdmr_common |= LSDMR_BSMA1516;
193 * Issue PRECHARGE ALL command.
195 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
198 ppcDcbf((unsigned long) sdram_addr);
202 * Issue 8 AUTO REFRESH commands.
204 for (idx = 0; idx < 8; idx++) {
205 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
208 ppcDcbf((unsigned long) sdram_addr);
213 * Issue 8 MODE-set command.
215 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
218 ppcDcbf((unsigned long) sdram_addr);
222 * Issue NORMAL OP command.
224 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
227 ppcDcbf((unsigned long) sdram_addr);
228 udelay(200); /* Overkill. Must wait > 200 bus cycles */
230 #endif /* enable SDRAM init */
233 #if defined(CONFIG_SYS_DRAM_TEST)
237 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
238 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
241 printf("Testing DRAM from 0x%08x to 0x%08x\n",
242 CONFIG_SYS_MEMTEST_START,
243 CONFIG_SYS_MEMTEST_END);
245 printf("DRAM test phase 1:\n");
246 for (p = pstart; p < pend; p++)
249 for (p = pstart; p < pend; p++) {
250 if (*p != 0xaaaaaaaa) {
251 printf ("DRAM test fails at: %08x\n", (uint) p);
256 printf("DRAM test phase 2:\n");
257 for (p = pstart; p < pend; p++)
260 for (p = pstart; p < pend; p++) {
261 if (*p != 0x55555555) {
262 printf ("DRAM test fails at: %08x\n", (uint) p);
267 printf("DRAM test passed.\n");
272 #if !defined(CONFIG_SPD_EEPROM)
273 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
274 /*************************************************************************
275 * fixed_sdram init -- doesn't use serial presence detect.
276 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
277 ************************************************************************/
278 long int fixed_sdram (void)
280 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
282 out_be32(&ddr->cs0_bnds, 0x0000007f);
283 out_be32(&ddr->cs1_bnds, 0x008000ff);
284 out_be32(&ddr->cs2_bnds, 0x00000000);
285 out_be32(&ddr->cs3_bnds, 0x00000000);
286 out_be32(&ddr->cs0_config, 0x80010101);
287 out_be32(&ddr->cs1_config, 0x80010101);
288 out_be32(&ddr->cs2_config, 0x00000000);
289 out_be32(&ddr->cs3_config, 0x00000000);
290 out_be32(&ddr->timing_cfg_3, 0x00000000);
291 out_be32(&ddr->timing_cfg_0, 0x00220802);
292 out_be32(&ddr->timing_cfg_1, 0x38377322);
293 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
294 out_be32(&ddr->sdram_cfg, 0x4300C000);
295 out_be32(&ddr->sdram_cfg_2, 0x24401000);
296 out_be32(&ddr->sdram_mode, 0x23C00542);
297 out_be32(&ddr->sdram_mode_2, 0x00000000);
298 out_be32(&ddr->sdram_interval, 0x05080100);
299 out_be32(&ddr->sdram_md_cntl, 0x00000000);
300 out_be32(&ddr->sdram_data_init, 0x00000000);
301 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
302 asm("sync;isync;msync");
305 #if defined (CONFIG_DDR_ECC)
306 /* Enable ECC checking */
307 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
309 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
312 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
317 static struct pci_controller pci1_hose;
318 #endif /* CONFIG_PCI1 */
321 static struct pci_controller pcie1_hose;
322 #endif /* CONFIG_PCIE1 */
324 int first_free_busno=0;
329 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
333 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
334 struct pci_controller *hose = &pci1_hose;
335 struct pci_region *r = hose->regions;
337 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
338 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
339 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
341 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
343 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
344 printf (" PCI host: %d bit, %s MHz, %s, %s\n",
346 (pci_speed == 33000000) ? "33" :
347 (pci_speed == 66000000) ? "66" : "unknown",
348 pci_clk_sel ? "sync" : "async",
349 pci_arb ? "arbiter" : "external-arbiter"
352 /* outbound memory */
354 CONFIG_SYS_PCI1_MEM_BASE,
355 CONFIG_SYS_PCI1_MEM_PHYS,
356 CONFIG_SYS_PCI1_MEM_SIZE,
361 CONFIG_SYS_PCI1_IO_BASE,
362 CONFIG_SYS_PCI1_IO_PHYS,
363 CONFIG_SYS_PCI1_IO_SIZE,
365 hose->region_count = r - hose->regions;
367 hose->first_busno=first_free_busno;
369 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
370 first_free_busno=hose->last_busno+1;
371 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
372 #ifdef CONFIG_PCIX_CHECK
373 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
375 if (CONFIG_SYS_CLK_FREQ < 66000000)
376 printf("PCI-X will only work at 66 MHz\n");
378 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
379 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
380 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
384 printf (" PCI: disabled\n");
388 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
391 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */
395 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
396 struct pci_controller *hose = &pcie1_hose;
397 struct pci_region *r = hose->regions;
399 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
401 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
402 printf ("\n PCIE at base address %x",
405 if (pci->pme_msg_det) {
406 pci->pme_msg_det = 0xffffffff;
407 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
411 /* outbound memory */
413 CONFIG_SYS_PCIE1_MEM_BASE,
414 CONFIG_SYS_PCIE1_MEM_PHYS,
415 CONFIG_SYS_PCIE1_MEM_SIZE,
420 CONFIG_SYS_PCIE1_IO_BASE,
421 CONFIG_SYS_PCIE1_IO_PHYS,
422 CONFIG_SYS_PCIE1_IO_SIZE,
425 hose->region_count = r - hose->regions;
427 hose->first_busno=first_free_busno;
429 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
430 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
432 first_free_busno=hose->last_busno+1;
435 printf (" PCIE: disabled\n");
439 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
444 int board_eth_init(bd_t *bis)
446 tsec_standard_init(bis);
448 return 0; /* otherwise cpu_eth_init gets run */
451 int last_stage_init(void)
456 #if defined(CONFIG_OF_BOARD_SETUP)
457 void ft_board_setup(void *blob, bd_t *bd)
459 ft_cpu_setup(blob, bd);
461 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
464 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);