2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 void local_bus_init(void);
43 void sdram_init(void);
44 long int fixed_sdram (void);
46 int board_early_init_f (void)
53 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
54 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
55 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
57 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
61 * Initialize local bus.
66 * Hack TSEC 3 and 4 IO voltages.
68 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
70 ecm->eedr = 0xffffffff; /* clear ecm errors */
71 ecm->eeer = 0xffffffff; /* enable ecm errors */
76 initdram(int board_type)
80 puts("Initializing\n");
82 #if defined(CONFIG_DDR_DLL)
85 * Work around to stabilize DDR DLL MSYNC_IN.
86 * Errata DDR9 seems to have been fixed.
87 * This is now the workaround for Errata DDR11:
88 * Override DLL = 1, Course Adj = 1, Tap Select = 0
91 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93 gur->ddrdllcr = 0x81000000;
94 asm("sync;isync;msync");
99 #if defined(CONFIG_SPD_EEPROM)
100 dram_size = fsl_ddr_sdram();
101 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
102 dram_size *= 0x100000;
104 dram_size = fixed_sdram ();
108 * SDRAM Initialization
117 * Initialize Local Bus
122 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
123 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
129 get_sys_info(&sysinfo);
130 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
131 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
133 gur->lbiuiplldcr1 = 0x00078080;
135 gur->lbiuiplldcr0 = 0x7c0f1bf0;
136 } else if (clkdiv == 8) {
137 gur->lbiuiplldcr0 = 0x6c0f1bf0;
138 } else if (clkdiv == 4) {
139 gur->lbiuiplldcr0 = 0x5c0f1bf0;
142 lbc->lcrr |= 0x00030000;
144 asm("sync;isync;msync");
146 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
147 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
151 * Initialize SDRAM memory on the Local Bus.
156 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
159 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
160 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
165 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
168 * Setup SDRAM Base and Option Registers
170 lbc->or3 = CONFIG_SYS_OR3_PRELIM;
173 lbc->br3 = CONFIG_SYS_BR3_PRELIM;
176 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
180 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
181 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
185 * MPC8548 uses "new" 15-16 style addressing.
187 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
188 lsdmr_common |= LSDMR_BSMA1516;
191 * Issue PRECHARGE ALL command.
193 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
196 ppcDcbf((unsigned long) sdram_addr);
200 * Issue 8 AUTO REFRESH commands.
202 for (idx = 0; idx < 8; idx++) {
203 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
206 ppcDcbf((unsigned long) sdram_addr);
211 * Issue 8 MODE-set command.
213 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
216 ppcDcbf((unsigned long) sdram_addr);
220 * Issue NORMAL OP command.
222 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
225 ppcDcbf((unsigned long) sdram_addr);
226 udelay(200); /* Overkill. Must wait > 200 bus cycles */
228 #endif /* enable SDRAM init */
231 #if defined(CONFIG_SYS_DRAM_TEST)
235 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
236 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
239 printf("Testing DRAM from 0x%08x to 0x%08x\n",
240 CONFIG_SYS_MEMTEST_START,
241 CONFIG_SYS_MEMTEST_END);
243 printf("DRAM test phase 1:\n");
244 for (p = pstart; p < pend; p++)
247 for (p = pstart; p < pend; p++) {
248 if (*p != 0xaaaaaaaa) {
249 printf ("DRAM test fails at: %08x\n", (uint) p);
254 printf("DRAM test phase 2:\n");
255 for (p = pstart; p < pend; p++)
258 for (p = pstart; p < pend; p++) {
259 if (*p != 0x55555555) {
260 printf ("DRAM test fails at: %08x\n", (uint) p);
265 printf("DRAM test passed.\n");
270 #if !defined(CONFIG_SPD_EEPROM)
271 /*************************************************************************
272 * fixed_sdram init -- doesn't use serial presence detect.
273 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
274 ************************************************************************/
275 long int fixed_sdram (void)
277 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
279 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
281 ddr->cs0_bnds = 0x0000007f;
282 ddr->cs1_bnds = 0x008000ff;
283 ddr->cs2_bnds = 0x00000000;
284 ddr->cs3_bnds = 0x00000000;
285 ddr->cs0_config = 0x80010101;
286 ddr->cs1_config = 0x80010101;
287 ddr->cs2_config = 0x00000000;
288 ddr->cs3_config = 0x00000000;
289 ddr->timing_cfg_3 = 0x00000000;
290 ddr->timing_cfg_0 = 0x00220802;
291 ddr->timing_cfg_1 = 0x38377322;
292 ddr->timing_cfg_2 = 0x0fa044C7;
293 ddr->sdram_cfg = 0x4300C000;
294 ddr->sdram_cfg_2 = 0x24401000;
295 ddr->sdram_mode = 0x23C00542;
296 ddr->sdram_mode_2 = 0x00000000;
297 ddr->sdram_interval = 0x05080100;
298 ddr->sdram_md_cntl = 0x00000000;
299 ddr->sdram_data_init = 0x00000000;
300 ddr->sdram_clk_cntl = 0x03800000;
301 asm("sync;isync;msync");
304 #if defined (CONFIG_DDR_ECC)
305 /* Enable ECC checking */
306 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
308 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
311 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
315 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
316 /* For some reason the Tundra PCI bridge shows up on itself as a
317 * different device. Work around that by refusing to configure it.
319 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
321 static struct pci_config_table pci_sbc8548_config_table[] = {
322 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
323 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
324 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
325 mpc85xx_config_via_usbide, {0,0,0}},
326 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
327 mpc85xx_config_via_usb, {0,0,0}},
328 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
329 mpc85xx_config_via_usb2, {0,0,0}},
330 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
331 mpc85xx_config_via_power, {0,0,0}},
332 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
333 mpc85xx_config_via_ac97, {0,0,0}},
337 static struct pci_controller pci1_hose = {
338 config_table: pci_sbc8548_config_table};
339 #endif /* CONFIG_PCI */
342 static struct pci_controller pci2_hose;
343 #endif /* CONFIG_PCI2 */
346 static struct pci_controller pcie1_hose;
347 #endif /* CONFIG_PCIE1 */
349 int first_free_busno=0;
354 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
358 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
359 struct pci_controller *hose = &pci1_hose;
360 struct pci_config_table *table;
361 struct pci_region *r = hose->regions;
363 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
364 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
365 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
367 uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
369 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
371 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
372 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
374 (pci_speed == 33333000) ? "33" :
375 (pci_speed == 66666000) ? "66" : "unknown",
376 pci_clk_sel ? "sync" : "async",
377 pci_agent ? "agent" : "host",
378 pci_arb ? "arbiter" : "external-arbiter"
381 /* outbound memory */
383 CONFIG_SYS_PCI1_MEM_BASE,
384 CONFIG_SYS_PCI1_MEM_PHYS,
385 CONFIG_SYS_PCI1_MEM_SIZE,
390 CONFIG_SYS_PCI1_IO_BASE,
391 CONFIG_SYS_PCI1_IO_PHYS,
392 CONFIG_SYS_PCI1_IO_SIZE,
394 hose->region_count = r - hose->regions;
396 /* relocate config table pointers */
397 hose->config_table = \
398 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
399 for (table = hose->config_table; table && table->vendor; table++)
400 table->config_device += gd->reloc_off;
402 hose->first_busno=first_free_busno;
404 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
405 first_free_busno=hose->last_busno+1;
406 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
407 #ifdef CONFIG_PCIX_CHECK
408 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
410 if (CONFIG_SYS_CLK_FREQ < 66000000)
411 printf("PCI-X will only work at 66 MHz\n");
413 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
414 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
415 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
419 printf (" PCI: disabled\n");
423 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
428 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
429 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
431 printf (" PCI2: 32 bit, 66 MHz, %s\n",
432 pci2_clk_sel ? "sync" : "async");
434 printf (" PCI2: disabled\n");
438 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
439 #endif /* CONFIG_PCI2 */
443 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
444 struct pci_controller *hose = &pcie1_hose;
445 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
446 struct pci_region *r = hose->regions;
448 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
450 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
451 printf ("\n PCIE connected to slot as %s (base address %x)",
452 pcie_ep ? "End Point" : "Root Complex",
455 if (pci->pme_msg_det) {
456 pci->pme_msg_det = 0xffffffff;
457 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
461 /* outbound memory */
463 CONFIG_SYS_PCIE1_MEM_BASE,
464 CONFIG_SYS_PCIE1_MEM_PHYS,
465 CONFIG_SYS_PCIE1_MEM_SIZE,
470 CONFIG_SYS_PCIE1_IO_BASE,
471 CONFIG_SYS_PCIE1_IO_PHYS,
472 CONFIG_SYS_PCIE1_IO_SIZE,
475 hose->region_count = r - hose->regions;
477 hose->first_busno=first_free_busno;
479 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
480 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
482 first_free_busno=hose->last_busno+1;
485 printf (" PCIE: disabled\n");
489 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
494 int last_stage_init(void)
499 #if defined(CONFIG_OF_BOARD_SETUP)
500 void ft_board_setup(void *blob, bd_t *bd)
502 ft_cpu_setup(blob, bd);
504 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
507 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);