1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <asm/fsl_law.h>
14 * LAW(Local Access Window) configuration:
16 * 0x0000_0000 0x0fff_ffff DDR 256M
17 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
18 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
19 * 0xe000_0000 0xe000_ffff CCSR 1M
20 * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
21 * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
22 * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
23 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
24 * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
25 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
27 * If swapped CS0/CS6 via JP12+SW2.8:
28 * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
29 * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
32 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
33 * If flash is 8M at default position (last 8M), no LAW needed.
36 struct law_entry law_table[] = {
37 #ifdef CONFIG_SYS_ALT_BOOT
38 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
40 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
42 #ifndef CONFIG_SPD_EEPROM
43 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
45 #ifdef CONFIG_SYS_LBC_SDRAM_BASE
46 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
47 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
49 /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
50 SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
54 int num_law_entries = ARRAY_SIZE(law_table);