board/sbc8548/ddr.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 static void
  16 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  17 {
  18         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  19 }
  20
  21 unsigned int fsl_ddr_get_mem_data_rate(void)
  22 {
  23         return get_ddr_freq(0);
  24 }
  25
  26 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  27                         unsigned int ctrl_num)
  28 {
  29         unsigned int i;
  30
  31         if (ctrl_num) {
  32                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  33                 return;
  34         }
  35
  36         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  37                 get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
  38         }
  39 }
  40
  41 void fsl_ddr_board_options(memctl_options_t *popts,
  42                                 dimm_params_t *pdimm,
  43                                 unsigned int ctrl_num)
  44 {
  45         /*
  46          * Factors to consider for clock adjust:
  47          *      - number of chips on bus
  48          *      - position of slot
  49          *      - DDR1 vs. DDR2?
  50          *      - ???
  51          *
  52          * This needs to be determined on a board-by-board basis.
  53          *      0110    3/4 cycle late
  54          *      0111    7/8 cycle late
  55          */
  56         popts->clk_adjust = 7;
  57
  58         /*
  59          * Factors to consider for CPO:
  60          *      - frequency
  61          *      - ddr1 vs. ddr2
  62          */
  63         popts->cpo_override = 10;
  64
  65         /*
  66          * Factors to consider for write data delay:
  67          *      - number of DIMMs
  68          *
  69          * 1 = 1/4 clock delay
  70          * 2 = 1/2 clock delay
  71          * 3 = 3/4 clock delay
  72          * 4 = 1   clock delay
  73          * 5 = 5/4 clock delay
  74          * 6 = 3/2 clock delay
  75          */
  76         popts->write_data_delay = 3;
  77
  78         /*
  79          * Factors to consider for half-strength driver enable:
  80          *      - number of DIMMs installed
  81          */
  82         popts->half_strength_driver_enable = 0;
  83 }