1 // SPDX-License-Identifier: GPL-2.0+
3 * sbc8349.c -- WindRiver SBC8349 board support.
4 * Copyright (c) 2006-2007 Wind River Systems, Inc.
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
11 #include <fdt_support.h>
15 #include <asm/bitops.h>
16 #include <asm/mpc8349_pci.h>
18 #include <spd_sdram.h>
20 #if defined(CONFIG_OF_LIBFDT)
21 #include <linux/libfdt.h>
23 #include <linux/delay.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 int fixed_sdram(void);
28 void sdram_init(void);
30 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
31 void ddr_enable_ecc(unsigned int dram_size);
34 #ifdef CONFIG_BOARD_EARLY_INIT_F
35 int board_early_init_f (void)
41 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
45 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
48 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
51 /* DDR SDRAM - Main SODIMM */
52 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
53 #if defined(CONFIG_SPD_EEPROM)
56 msize = fixed_sdram();
59 * Initialize SDRAM if it is on local bus.
63 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
65 * Initialize and enable DDR ECC.
67 ddr_enable_ecc(msize * 1024 * 1024);
69 /* set total bus SDRAM size(bytes) -- DDR */
70 gd->ram_size = msize * 1024 * 1024;
75 #if !defined(CONFIG_SPD_EEPROM)
76 /*************************************************************************
77 * fixed sdram init -- doesn't use serial presence detect.
78 ************************************************************************/
81 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
82 u32 msize = CONFIG_SYS_DDR_SIZE;
83 u32 ddr_size = msize << 20; /* DDR size in bytes */
84 u32 ddr_size_log2 = __ilog2(msize);
86 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
87 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
89 #if (CONFIG_SYS_DDR_SIZE != 256)
90 #warning Currently any ddr size other than 256 is not supported
93 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
94 #warning Chip select bounds is only configurable in 16MB increments
96 im->ddr.csbnds[2].csbnds =
97 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
98 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
99 CSBNDS_EA_SHIFT) & CSBNDS_EA);
100 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
102 /* currently we use only one CS, so disable the other banks */
103 im->ddr.cs_config[0] = 0;
104 im->ddr.cs_config[1] = 0;
105 im->ddr.cs_config[3] = 0;
107 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
108 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
112 #if defined(CONFIG_DDR_2T_TIMING)
115 | SDRAM_CFG_SDRAM_TYPE_DDR1;
116 #if defined (CONFIG_DDR_32BIT)
117 /* for 32-bit mode burst length is 8 */
118 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
120 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
122 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
125 /* enable DDR controller */
126 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
129 #endif/*!CONFIG_SYS_SPD_EEPROM*/
132 int checkboard (void)
134 puts("Board: Wind River SBC834x\n");
139 * if board is fitted with SDRAM
141 #if defined(CONFIG_SYS_BR2_PRELIM) \
142 && defined(CONFIG_SYS_OR2_PRELIM) \
143 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
144 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
146 * Initialize SDRAM memory on the Local Bus.
149 void sdram_init(void)
151 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
152 volatile fsl_lbc_t *lbc = &immap->im_lbc;
153 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
154 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
155 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
156 LSDMR_WRC3 | LSDMR_CL3;
158 puts("\n SDRAM on Local Bus: ");
159 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
162 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
165 /* setup mtrpt, lsrt and lbcr for LB bus */
166 lbc->lbcr = 0x00000000;
167 /* LB refresh timer prescal, 266MHz/32 */
168 lbc->mrtpr = 0x20000000;
169 /* LB sdram refresh timer, about 6us */
170 lbc->lsrt = 0x32000000;
174 * Configure the SDRAM controller Machine Mode Register.
176 /* 0x40636733; normal operation */
177 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
179 /* 0x68636733; precharge all the banks */
180 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
185 /* 0x48636733; auto refresh */
186 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
213 /* 0x58636733; mode register write operation */
214 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
219 /* 0x40636733; normal operation */
220 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
226 void sdram_init(void)
228 puts(" SDRAM on Local Bus: Disabled in config\n");
232 #if defined(CONFIG_OF_BOARD_SETUP)
233 int ft_board_setup(void *blob, bd_t *bd)
235 ft_cpu_setup(blob, bd);
237 ft_pci_setup(blob, bd);