2 * Memory setup for SMDKV310 board based on EXYNOS4210
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #ifdef CONFIG_CLK_800_330_165
34 #ifdef CONFIG_CLK_1000_200_200
37 #ifdef CONFIG_CLK_1000_330_165
40 #ifdef CONFIG_CLK_1000_400_200
44 .globl mem_ctrl_asm_init
48 * Async bridge configuration at CPU_core:
57 ldr r0, =EXYNOS4_MIU_BASE @0x10600000
58 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
60 str r1, [r0, #0x400] @MIU_INTLV_CONFIG
62 str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
64 str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
66 str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
68 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
70 str r1, [r0, #0x400] @MIU_INTLV_CONFIG
72 str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
74 str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
76 str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
78 #ifdef CONFIG_MIU_LINEAR
80 str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
82 str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
84 str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
86 str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
88 str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
92 ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
95 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
98 str r1, [r0, #0x44] @DMC_PHYZQCONTROL
105 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
107 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
110 str r1, [r0, #0x18] @DMC_PHYCONTROL0
112 str r1, [r0, #0x18] @DMC_PHYCONTROL0
114 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
116 str r1, [r0, #0x18] @DMC_PHYCONTROL0
119 str r1, [r0, #0x20] @DMC_PHYCONTROL2
122 str r1, [r0, #0x00] @DMC_CONCONTROL
124 str r1, [r0, #0x04] @DMC_MEMCONTROL]
126 #ifdef CONFIG_MIU_LINEAR
128 str r1, [r0, #0x08] @DMC_MEMCONFIG0
130 str r1, [r0, #0x0C] @DMC_MEMCONFIG1
131 #else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
133 str r1, [r0, #0x08] @DMC_MEMCONFIG0
135 str r1, [r0, #0x0C] @DMC_MEMCONFIG1
139 str r1, [r0, #0x14] @DMC_PRECHCONFIG
142 str r1, [r0, #0x30] @DMC_TIMINGAREF
146 str r1, [r0, #0x34] @DMC_TIMINGROW
148 str r1, [r0, #0x38] @DMC_TIMINGDATA
150 str r1, [r0, #0x3C] @DMC_TIMINGPOWER
154 str r1, [r0, #0x34] @DMC_TIMINGROW
156 str r1, [r0, #0x38] @DMC_TIMINGDATA
158 str r1, [r0, #0x3C] @DMC_TIMINGPOWER
161 str r1, [r0, #0x10] @DMC_DIRECTCMD
168 str r1, [r0, #0x10] @DMC_DIRECTCMD
170 str r1, [r0, #0x10] @DMC_DIRECTCMD
172 str r1, [r0, #0x10] @DMC_DIRECTCMD
174 str r1, [r0, #0x10] @DMC_DIRECTCMD
181 str r1, [r0, #0x10] @DMC_DIRECTCMD
188 str r1, [r0, #0x10] @DMC_DIRECTCMD
195 str r1, [r0, #0x10] @DMC_DIRECTCMD
197 str r1, [r0, #0x10] @DMC_DIRECTCMD
199 str r1, [r0, #0x10] @DMC_DIRECTCMD
201 str r1, [r0, #0x10] @DMC_DIRECTCMD
208 str r1, [r0, #0x10] @DMC_DIRECTCMD
215 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
217 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
224 ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
227 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
230 str r1, [r0, #0x44] @DMC_PHYZQCONTROL
237 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
239 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
242 str r1, [r0, #0x18] @DMC_PHYCONTROL0
244 str r1, [r0, #0x18] @DMC_PHYCONTROL0
246 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
248 str r1, [r0, #0x18] @DMC_PHYCONTROL0
251 str r1, [r0, #0x20] @DMC_PHYCONTROL2
254 str r1, [r0, #0x00] @DMC_CONCONTROL
256 str r1, [r0, #0x04] @DMC_MEMCONTROL]
258 #ifdef CONFIG_MIU_LINEAR
260 str r1, [r0, #0x08] @DMC_MEMCONFIG0
262 str r1, [r0, #0x0C] @DMC_MEMCONFIG1
263 #else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
265 str r1, [r0, #0x08] @DMC_MEMCONFIG0
267 str r1, [r0, #0x0C] @DMC_MEMCONFIG1
271 str r1, [r0, #0x14] @DMC_PRECHCONFIG
274 str r1, [r0, #0x30] @DMC_TIMINGAREF
278 str r1, [r0, #0x34] @DMC_TIMINGROW
280 str r1, [r0, #0x38] @DMC_TIMINGDATA
282 str r1, [r0, #0x3C] @DMC_TIMINGPOWER
286 str r1, [r0, #0x34] @DMC_TIMINGROW
288 str r1, [r0, #0x38] @DMC_TIMINGDATA
290 str r1, [r0, #0x3C] @DMC_TIMINGPOWER
294 str r1, [r0, #0x10] @DMC_DIRECTCMD
301 str r1, [r0, #0x10] @DMC_DIRECTCMD
303 str r1, [r0, #0x10] @DMC_DIRECTCMD
305 str r1, [r0, #0x10] @DMC_DIRECTCMD
307 str r1, [r0, #0x10] @DMC_DIRECTCMD
314 str r1, [r0, #0x10] @DMC_DIRECTCMD
321 str r1, [r0, #0x10] @DMC_DIRECTCMD
328 str r1, [r0, #0x10] @DMC_DIRECTCMD
330 str r1, [r0, #0x10] @DMC_DIRECTCMD
332 str r1, [r0, #0x10] @DMC_DIRECTCMD
334 str r1, [r0, #0x10] @DMC_DIRECTCMD
341 str r1, [r0, #0x10] @DMC_DIRECTCMD
348 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
350 str r1, [r0, #0x1C] @DMC_PHYCONTROL1
356 /* turn on DREX0, DREX1 */
357 ldr r0, =0x10400000 @APB_DMC_0_BASE
359 str r1, [r0, #0x00] @DMC_CONCONTROL
361 ldr r0, =0x10410000 @APB_DMC_1_BASE
363 str r1, [r0, #0x00] @DMC_CONCONTROL