1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009 Samsung Electronics
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Minkyu Kang <mk7.kang@samsung.com>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/power.h>
22 /* r5 has always zero */
25 ldr r8, =S5PC100_GPIO_BASE
27 /* Disable Watchdog */
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
33 ldr r0, =S5PC100_SROMC_BASE
37 /* S5PC100 has 3 groups of interrupt sources */
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
42 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
46 str r3, [r2, #0x14] @INTENCLEAR
48 /* Set all interrupts as IRQ */
49 str r5, [r0, #0xc] @INTSELECT
50 str r5, [r1, #0xc] @INTSELECT
51 str r5, [r2, #0xc] @INTSELECT
53 /* Pending Interrupt Clear */
54 str r5, [r0, #0xf00] @INTADDRESS
55 str r5, [r1, #0xf00] @INTADDRESS
56 str r5, [r2, #0xf00] @INTADDRESS
69 * system_clock_init: Initialize core clock and bus clock.
70 * void system_clock_init(void)
73 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
75 /* Set Clock divider */
84 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
85 str r1, [r8, #0x000] @ APLL_LOCK
86 str r1, [r8, #0x004] @ MPLL_LOCK
87 str r1, [r8, #0x008] @ EPLL_LOCK
88 str r1, [r8, #0x00C] @ HPLL_LOCK
91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
103 /* Set Source Clock */
104 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
105 str r1, [r8, #0x200] @ CLK_SRC0
107 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
108 str r1, [r8, #0x204] @ CLK_SRC1
110 ldr r1, =0x9000 @ ARMCLK/4
111 str r1, [r8, #0x400] @ CLK_OUT
113 /* wait at least 200us to stablize all clock */
121 * uart_asm_init: Initialize UART's pins
126 str r1, [r0, #0x0] @ GPA0_CON
128 str r1, [r0, #0x20] @ GPA1_CON
133 * tzpc_asm_init: Initialize TZPC