2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the Samsung SMDK2410 by
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
12 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
41 #elif defined(CONFIG_SERIAL2)
42 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
44 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
55 ldr r0, =ELFIN_GPIO_BASE
57 str r1, [r0, #GPNCON_OFFSET]
60 str r1, [r0, #GPNPUD_OFFSET]
63 str r1, [r0, #GPNDAT_OFFSET]
65 /* Disable Watchdog */
66 ldr r0, =0x7e000000 @0x7e004000
71 /* External interrupt pending clear */
72 ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
76 ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
77 ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
79 /* Disable all interrupts (VIC0 and VIC1) */
81 str r3, [r0, #oINTMSK]
82 str r3, [r1, #oINTMSK]
84 /* Set all interrupts as IRQ */
86 str r3, [r0, #oINTMOD]
87 str r3, [r1, #oINTMOD]
89 /* Pending Interrupt Clear */
91 str r3, [r0, #oVECTADDR]
92 str r3, [r1, #oVECTADDR]
94 /* init system clock */
97 #ifndef CONFIG_NAND_SPL
102 #ifdef CONFIG_BOOT_NAND
103 /* simple init for NAND */
109 /* Wakeup support. Don't know if it's going to be used, untested. */
110 ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
112 bic r1, r1, #0xfffffff7
122 /* Clear wakeup status register */
123 ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
128 ldr r0, =ELFIN_GPIO_BASE
130 str r1, [r0, #GPNDAT_OFFSET]
132 /* Load return address and jump to kernel */
133 ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
134 /* r1 = physical address of s3c6400_cpu_resume function */
136 /* Jump to kernel (sleep-s3c6400.S) */
141 * system_clock_init: Initialize core clock and bus clock.
142 * void system_clock_init(void)
145 ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
147 #ifdef CONFIG_SYNC_MODE
148 ldr r1, [r0, #OTHERS_OFFSET]
151 str r1, [r0, #OTHERS_OFFSET]
161 str r1, [r0, #OTHERS_OFFSET]
164 ldr r1, [r0, #OTHERS_OFFSET]
169 #else /* ASYNC Mode */
177 * This was unconditional in original Samsung sources, but it doesn't
178 * seem to make much sense on S3C6400.
180 #ifndef CONFIG_S3C6400
181 ldr r1, [r0, #OTHERS_OFFSET]
184 str r1, [r0, #OTHERS_OFFSET]
187 ldr r1, [r0, #OTHERS_OFFSET]
193 ldr r1, [r0, #OTHERS_OFFSET]
195 str r1, [r0, #OTHERS_OFFSET]
200 str r1, [r0, #APLL_LOCK_OFFSET]
201 str r1, [r0, #MPLL_LOCK_OFFSET]
203 /* Set Clock Divider */
204 ldr r1, [r0, #CLK_DIV0_OFFSET]
210 str r1, [r0, #CLK_DIV0_OFFSET]
213 str r1, [r0, #APLL_CON_OFFSET]
215 str r1, [r0, #MPLL_CON_OFFSET]
217 /* FOUT of EPLL is 96MHz */
219 str r1, [r0, #EPLL_CON0_OFFSET]
221 str r1, [r0, #EPLL_CON1_OFFSET]
223 /* APLL, MPLL, EPLL select to Fout */
224 ldr r1, [r0, #CLK_SRC_OFFSET]
226 str r1, [r0, #CLK_SRC_OFFSET]
228 /* wait at least 200us to stablize all clock */
233 /* Synchronization for VIC port */
234 #if defined(CONFIG_SYNC_MODE)
235 ldr r1, [r0, #OTHERS_OFFSET]
237 str r1, [r0, #OTHERS_OFFSET]
238 #elif !defined(CONFIG_S3C6400)
239 /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
240 ldr r1, [r0, #OTHERS_OFFSET]
242 str r1, [r0, #OTHERS_OFFSET]
247 #ifndef CONFIG_NAND_SPL
249 * uart_asm_init: Initialize UART's pins
252 /* set GPIO to enable UART */
253 ldr r0, =ELFIN_GPIO_BASE
255 str r1, [r0, #GPACON_OFFSET]
259 #ifdef CONFIG_BOOT_NAND
261 * NAND Interface init for SMDK6400
264 ldr r0, =ELFIN_NAND_BASE
265 ldr r1, [r0, #NFCONF_OFFSET]
268 str r1, [r0, #NFCONF_OFFSET]
270 ldr r1, [r0, #NFCONT_OFFSET]
272 str r1, [r0, #NFCONT_OFFSET]
277 #ifdef CONFIG_ENABLE_MMU
279 * MMU Table for SMDK6400
282 /* form a first-level section entry */
283 .macro FL_SECTION_ENTRY base,ap,d,c,b
284 .word (\base << 20) | (\ap << 10) | \
285 (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
288 .section .mmudata, "a"
290 /* the following alignment creates the mmu table at address 0x4000. */
294 /* 1:1 mapping for debugging */
296 FL_SECTION_ENTRY __base, 3, 0, 0, 0
297 .set __base, __base + 1
300 /* access is not allowed. */
305 /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
308 FL_SECTION_ENTRY __base, 3, 0, 1, 1
309 .set __base, __base + 1
312 /* access is not allowed. */