2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/clk.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/spl.h>
31 #include <asm/arch/dwmmc.h>
33 #include "clock_init.h"
36 #define FSYS1_MMC0_DIV_MASK 0xff0f
37 #define FSYS1_MMC0_DIV_VAL 0x0701
39 DECLARE_GLOBAL_DATA_PTR;
41 struct arm_clk_ratios arm_clk_ratios[] = {
51 .pclk_dbg_ratio = 0x1,
66 .pclk_dbg_ratio = 0x1,
81 .pclk_dbg_ratio = 0x1,
96 .pclk_dbg_ratio = 0x1,
103 .arm_freq_mhz = 1400,
111 .pclk_dbg_ratio = 0x1,
118 .arm_freq_mhz = 1700,
126 .pclk_dbg_ratio = 0x1,
134 struct mem_timings mem_timings[] = {
136 .mem_manuf = MEM_MANUF_ELPIDA,
137 .mem_type = DDR_MODE_DDR3,
138 .frequency_mhz = 800,
158 .pclk_cdrex_ratio = 0x5,
160 0x00020018, 0x00030000, 0x00010042, 0x00000d70
162 .timing_ref = 0x000000bb,
163 .timing_row = 0x8c36650e,
164 .timing_data = 0x3630580b,
165 .timing_power = 0x41000a44,
166 .phy0_dqs = 0x08080808,
167 .phy1_dqs = 0x08080808,
168 .phy0_dq = 0x08080808,
169 .phy1_dq = 0x08080808,
172 .phy0_pulld_dqs = 0xf,
173 .phy1_pulld_dqs = 0xf,
175 .lpddr3_ctrl_phy_reset = 0x1,
176 .ctrl_start_point = 0x10,
198 * Dynamic Clock: Always Running
199 * Memory Burst length: 8
201 * Memory Bus width: 32 bit
203 * Additional Latancy for PLL: 0 Cycle
205 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
206 DMC_MEMCONTROL_DPWRDN_DISABLE |
207 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
208 DMC_MEMCONTROL_TP_DISABLE |
209 DMC_MEMCONTROL_DSREF_ENABLE |
210 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
211 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
212 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
213 DMC_MEMCONTROL_NUM_CHIP_1 |
214 DMC_MEMCONTROL_BL_8 |
215 DMC_MEMCONTROL_PZQ_DISABLE |
216 DMC_MEMCONTROL_MRR_BYTE_7_0,
217 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
218 DMC_MEMCONFIGx_CHIP_COL_10 |
219 DMC_MEMCONFIGx_CHIP_ROW_15 |
220 DMC_MEMCONFIGx_CHIP_BANK_8,
221 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
222 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
223 .prechconfig_tp_cnt = 0xff,
226 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
227 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
228 DMC_CONCONTROL_RD_FETCH_DISABLE |
229 DMC_CONCONTROL_EMPTY_DISABLE |
230 DMC_CONCONTROL_AREF_EN_DISABLE |
231 DMC_CONCONTROL_IO_PD_CON_DISABLE,
233 .chips_per_channel = 2,
234 .chips_to_configure = 1,
236 .impedance = IMP_OUTPUT_DRV_30_OHM,
237 .gate_leveling_enable = 0,
239 .mem_manuf = MEM_MANUF_SAMSUNG,
240 .mem_type = DDR_MODE_DDR3,
241 .frequency_mhz = 800,
261 .pclk_cdrex_ratio = 0x5,
263 0x00020018, 0x00030000, 0x00010000, 0x00000d70
265 .timing_ref = 0x000000bb,
266 .timing_row = 0x8c36650e,
267 .timing_data = 0x3630580b,
268 .timing_power = 0x41000a44,
269 .phy0_dqs = 0x08080808,
270 .phy1_dqs = 0x08080808,
271 .phy0_dq = 0x08080808,
272 .phy1_dq = 0x08080808,
275 .phy0_pulld_dqs = 0xf,
276 .phy1_pulld_dqs = 0xf,
278 .lpddr3_ctrl_phy_reset = 0x1,
279 .ctrl_start_point = 0x10,
301 * Dynamic Clock: Always Running
302 * Memory Burst length: 8
304 * Memory Bus width: 32 bit
306 * Additional Latancy for PLL: 0 Cycle
308 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
309 DMC_MEMCONTROL_DPWRDN_DISABLE |
310 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
311 DMC_MEMCONTROL_TP_DISABLE |
312 DMC_MEMCONTROL_DSREF_ENABLE |
313 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
314 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
315 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
316 DMC_MEMCONTROL_NUM_CHIP_1 |
317 DMC_MEMCONTROL_BL_8 |
318 DMC_MEMCONTROL_PZQ_DISABLE |
319 DMC_MEMCONTROL_MRR_BYTE_7_0,
320 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
321 DMC_MEMCONFIGx_CHIP_COL_10 |
322 DMC_MEMCONFIGx_CHIP_ROW_15 |
323 DMC_MEMCONFIGx_CHIP_BANK_8,
324 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
325 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
326 .prechconfig_tp_cnt = 0xff,
329 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
330 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
331 DMC_CONCONTROL_RD_FETCH_DISABLE |
332 DMC_CONCONTROL_EMPTY_DISABLE |
333 DMC_CONCONTROL_AREF_EN_DISABLE |
334 DMC_CONCONTROL_IO_PD_CON_DISABLE,
336 .chips_per_channel = 2,
337 .chips_to_configure = 1,
339 .impedance = IMP_OUTPUT_DRV_40_OHM,
340 .gate_leveling_enable = 1,
345 * Get the required memory type and speed (SPL version).
347 * In SPL we have no device tree, so we use the machine parameters
349 * @param mem_type Returns memory type
350 * @param frequency_mhz Returns memory speed in MHz
351 * @param arm_freq Returns ARM clock speed in MHz
352 * @param mem_manuf Return Memory Manufacturer name
353 * @return 0 if all ok
355 static int clock_get_mem_selection(enum ddr_mode *mem_type,
356 unsigned *frequency_mhz, unsigned *arm_freq,
357 enum mem_manuf *mem_manuf)
359 struct spl_machine_param *params;
361 params = spl_get_machine_params();
362 *mem_type = params->mem_type;
363 *frequency_mhz = params->frequency_mhz;
364 *arm_freq = params->arm_freq_mhz;
365 *mem_manuf = params->mem_manuf;
370 /* Get the ratios for setting ARM clock */
371 struct arm_clk_ratios *get_arm_ratios(void)
373 struct arm_clk_ratios *arm_ratio;
374 enum ddr_mode mem_type;
375 enum mem_manuf mem_manuf;
376 unsigned frequency_mhz, arm_freq;
379 if (clock_get_mem_selection(&mem_type, &frequency_mhz,
380 &arm_freq, &mem_manuf))
382 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
384 if (arm_ratio->arm_freq_mhz == arm_freq)
388 /* will hang if failed to find clock ratio */
395 struct mem_timings *clock_get_mem_timings(void)
397 struct mem_timings *mem;
398 enum ddr_mode mem_type;
399 enum mem_manuf mem_manuf;
400 unsigned frequency_mhz, arm_freq;
403 if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
404 &arm_freq, &mem_manuf)) {
405 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
407 if (mem->mem_type == mem_type &&
408 mem->frequency_mhz == frequency_mhz &&
409 mem->mem_manuf == mem_manuf)
414 /* will hang if failed to find memory timings */
421 void system_clock_init()
423 struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
424 struct mem_timings *mem;
425 struct arm_clk_ratios *arm_clk_ratio;
428 mem = clock_get_mem_timings();
429 arm_clk_ratio = get_arm_ratios();
431 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
433 val = readl(&clk->mux_stat_cpu);
434 } while ((val | MUX_APLL_SEL_MASK) != val);
436 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
438 val = readl(&clk->mux_stat_core1);
439 } while ((val | MUX_MPLL_SEL_MASK) != val);
441 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
442 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
443 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
444 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
445 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
448 val = readl(&clk->mux_stat_top2);
449 } while ((val | tmp) != val);
451 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
453 val = readl(&clk->mux_stat_cdrex);
454 } while ((val | MUX_BPLL_SEL_MASK) != val);
457 writel(APLL_LOCK_VAL, &clk->apll_lock);
459 writel(MPLL_LOCK_VAL, &clk->mpll_lock);
461 writel(BPLL_LOCK_VAL, &clk->bpll_lock);
463 writel(CPLL_LOCK_VAL, &clk->cpll_lock);
465 writel(GPLL_LOCK_VAL, &clk->gpll_lock);
467 writel(EPLL_LOCK_VAL, &clk->epll_lock);
469 writel(VPLL_LOCK_VAL, &clk->vpll_lock);
471 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
473 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
475 val = readl(&clk->mux_stat_cpu);
476 } while ((val | HPM_SEL_SCLK_MPLL) != val);
478 val = arm_clk_ratio->arm2_ratio << 28
479 | arm_clk_ratio->apll_ratio << 24
480 | arm_clk_ratio->pclk_dbg_ratio << 20
481 | arm_clk_ratio->atb_ratio << 16
482 | arm_clk_ratio->periph_ratio << 12
483 | arm_clk_ratio->acp_ratio << 8
484 | arm_clk_ratio->cpud_ratio << 4
485 | arm_clk_ratio->arm_ratio;
486 writel(val, &clk->div_cpu0);
488 val = readl(&clk->div_stat_cpu0);
491 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
493 val = readl(&clk->div_stat_cpu1);
497 writel(APLL_CON1_VAL, &clk->apll_con1);
498 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
499 arm_clk_ratio->apll_sdiv);
500 writel(val, &clk->apll_con0);
501 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
505 writel(MPLL_CON1_VAL, &clk->mpll_con1);
506 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
507 writel(val, &clk->mpll_con0);
508 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
512 writel(BPLL_CON1_VAL, &clk->bpll_con1);
513 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
514 writel(val, &clk->bpll_con0);
515 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
519 writel(CPLL_CON1_VAL, &clk->cpll_con1);
520 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
521 writel(val, &clk->cpll_con0);
522 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
526 writel(GPLL_CON1_VAL, &clk->gpll_con1);
527 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
528 writel(val, &clk->gpll_con0);
529 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
533 writel(EPLL_CON2_VAL, &clk->epll_con2);
534 writel(EPLL_CON1_VAL, &clk->epll_con1);
535 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
536 writel(val, &clk->epll_con0);
537 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
541 writel(VPLL_CON2_VAL, &clk->vpll_con2);
542 writel(VPLL_CON1_VAL, &clk->vpll_con1);
543 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
544 writel(val, &clk->vpll_con0);
545 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
548 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
549 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
550 while (readl(&clk->div_stat_core0) != 0)
553 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
554 while (readl(&clk->div_stat_core1) != 0)
557 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
558 while (readl(&clk->div_stat_sysrgt) != 0)
561 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
562 while (readl(&clk->div_stat_acp) != 0)
565 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
566 while (readl(&clk->div_stat_syslft) != 0)
569 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
570 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
571 writel(TOP2_VAL, &clk->src_top2);
572 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
574 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
575 while (readl(&clk->div_stat_top0))
578 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
579 while (readl(&clk->div_stat_top1))
582 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
584 val = readl(&clk->mux_stat_lex);
585 if (val == (val | 1))
589 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
590 while (readl(&clk->div_stat_lex))
593 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
594 while (readl(&clk->div_stat_r0x))
597 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
598 while (readl(&clk->div_stat_r0x))
601 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
602 while (readl(&clk->div_stat_r1x))
605 writel(CLK_REG_DISABLE, &clk->src_cdrex);
607 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
608 while (readl(&clk->div_stat_cdrex))
611 val = readl(&clk->src_cpu);
612 val |= CLK_SRC_CPU_VAL;
613 writel(val, &clk->src_cpu);
615 val = readl(&clk->src_top2);
616 val |= CLK_SRC_TOP2_VAL;
617 writel(val, &clk->src_top2);
619 val = readl(&clk->src_core1);
620 val |= CLK_SRC_CORE1_VAL;
621 writel(val, &clk->src_core1);
623 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
624 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
625 while (readl(&clk->div_stat_fsys0))
628 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
629 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
630 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
631 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
632 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
633 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
634 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
635 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
637 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
638 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
640 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
641 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
642 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
643 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
645 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
646 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
647 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
648 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
649 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
651 /* FIMD1 SRC CLK SELECTION */
652 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
654 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
655 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
656 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
657 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
658 writel(val, &clk->div_fsys2);
661 void clock_init_dp_clock(void)
663 struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
665 /* DP clock enable */
666 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
668 /* We run DP at 267 Mhz */
669 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
673 * Set clock divisor value for booting from EMMC.
674 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
676 void emmc_boot_clk_div_set(void)
678 struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
679 unsigned int div_mmc;
681 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
682 div_mmc |= FSYS1_MMC0_DIV_VAL;
683 writel(div_mmc, (unsigned int) &clk->div_fsys1);