2 * Machine Specific Values for ORIGEN board based on S5PV310
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _ORIGEN_SETUP_H
26 #define _ORIGEN_SETUP_H
30 #include <asm/arch/cpu.h>
32 /* Offsets of clock registers (sources and dividers) */
33 #define CLK_SRC_CPU_OFFSET 0x14200
34 #define CLK_DIV_CPU0_OFFSET 0x14500
35 #define CLK_DIV_CPU1_OFFSET 0x14504
37 #define CLK_SRC_DMC_OFFSET 0x10200
38 #define CLK_DIV_DMC0_OFFSET 0x10500
39 #define CLK_DIV_DMC1_OFFSET 0x10504
41 #define CLK_SRC_TOP0_OFFSET 0xC210
42 #define CLK_SRC_TOP1_OFFSET 0xC214
43 #define CLK_DIV_TOP_OFFSET 0xC510
45 #define CLK_SRC_LEFTBUS_OFFSET 0x4200
46 #define CLK_DIV_LEFTBUS_OFFSET 0x4500
48 #define CLK_SRC_RIGHTBUS_OFFSET 0x8200
49 #define CLK_DIV_RIGHTBUS_OFFSET 0x8500
51 #define CLK_SRC_FSYS_OFFSET 0xC240
52 #define CLK_DIV_FSYS1_OFFSET 0xC544
53 #define CLK_DIV_FSYS2_OFFSET 0xC548
54 #define CLK_DIV_FSYS3_OFFSET 0xC54C
56 #define CLK_SRC_PERIL0_OFFSET 0xC250
57 #define CLK_DIV_PERIL0_OFFSET 0xC550
59 #define CLK_SRC_LCD0_OFFSET 0xC234
61 #define APLL_LOCK_OFFSET 0x14000
62 #define MPLL_LOCK_OFFSET 0x14008
63 #define APLL_CON0_OFFSET 0x14100
64 #define APLL_CON1_OFFSET 0x14104
65 #define MPLL_CON0_OFFSET 0x14108
66 #define MPLL_CON1_OFFSET 0x1410C
68 #define EPLL_LOCK_OFFSET 0xC010
69 #define VPLL_LOCK_OFFSET 0xC020
70 #define EPLL_CON0_OFFSET 0xC110
71 #define EPLL_CON1_OFFSET 0xC114
72 #define VPLL_CON0_OFFSET 0xC120
73 #define VPLL_CON1_OFFSET 0xC124
75 /* DMC: DRAM Controllor Register offsets */
76 #define DMC_CONCONTROL 0x00
77 #define DMC_MEMCONTROL 0x04
78 #define DMC_MEMCONFIG0 0x08
79 #define DMC_MEMCONFIG1 0x0C
80 #define DMC_DIRECTCMD 0x10
81 #define DMC_PRECHCONFIG 0x14
82 #define DMC_PHYCONTROL0 0x18
83 #define DMC_PHYCONTROL1 0x1C
84 #define DMC_PHYCONTROL2 0x20
85 #define DMC_TIMINGAREF 0x30
86 #define DMC_TIMINGROW 0x34
87 #define DMC_TIMINGDATA 0x38
88 #define DMC_TIMINGPOWER 0x3C
89 #define DMC_PHYZQCONTROL 0x44
91 /* Bus Configuration Register Address */
92 #define ASYNC_CONFIG 0x10010350
94 /* MIU Config Register Offsets*/
95 #define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
96 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
98 /* Offset for inform registers */
99 #define INFORM0_OFFSET 0x800
100 #define INFORM1_OFFSET 0x804
102 /* GPIO Offsets for UART: GPIO Contol Register */
103 #define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
104 #define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
106 /* UART Register offsets */
107 #define ULCON_OFFSET 0x00
108 #define UCON_OFFSET 0x04
109 #define UFCON_OFFSET 0x08
110 #define UBRDIV_OFFSET 0x28
111 #define UFRACVAL_OFFSET 0x2C
113 /* TZPC : Register Offsets */
114 #define TZPC0_BASE 0x10110000
115 #define TZPC1_BASE 0x10120000
116 #define TZPC2_BASE 0x10130000
117 #define TZPC3_BASE 0x10140000
118 #define TZPC4_BASE 0x10150000
119 #define TZPC5_BASE 0x10160000
121 #define TZPC_DECPROT0SET_OFFSET 0x804
122 #define TZPC_DECPROT1SET_OFFSET 0x810
123 #define TZPC_DECPROT2SET_OFFSET 0x81C
124 #define TZPC_DECPROT3SET_OFFSET 0x828
127 #define MUX_HPM_SEL_MOUTAPLL 0x0
128 #define MUX_HPM_SEL_SCLKMPLL 0x1
129 #define MUX_CORE_SEL_MOUTAPLL 0x0
130 #define MUX_CORE_SEL_SCLKMPLL 0x1
131 #define MUX_MPLL_SEL_FILPLL 0x0
132 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
133 #define MUX_APLL_SEL_FILPLL 0x0
134 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
135 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
136 | (MUX_CORE_SEL_MOUTAPLL << 16) \
137 | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
138 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
141 #define APLL_RATIO 0x0
142 #define PCLK_DBG_RATIO 0x1
143 #define ATB_RATIO 0x3
144 #define PERIPH_RATIO 0x3
145 #define COREM1_RATIO 0x7
146 #define COREM0_RATIO 0x3
147 #define CORE_RATIO 0x0
148 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
149 | (PCLK_DBG_RATIO << 20) \
150 | (ATB_RATIO << 16) \
151 | (PERIPH_RATIO << 12) \
152 | (COREM1_RATIO << 8) \
153 | (COREM0_RATIO << 4) \
157 #define HPM_RATIO 0x0
158 #define COPY_RATIO 0x3
159 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
162 #define MUX_PWI_SEL_XXTI 0x0
163 #define MUX_PWI_SEL_XUSBXTI 0x1
164 #define MUX_PWI_SEL_SCLK_HDMI24M 0x2
165 #define MUX_PWI_SEL_SCLK_USBPHY0 0x3
166 #define MUX_PWI_SEL_SCLK_USBPHY1 0x4
167 #define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
168 #define MUX_PWI_SEL_SCLKMPLL 0x6
169 #define MUX_PWI_SEL_SCLKEPLL 0x7
170 #define MUX_PWI_SEL_SCLKVPLL 0x8
171 #define MUX_DPHY_SEL_SCLKMPLL 0x0
172 #define MUX_DPHY_SEL_SCLKAPLL 0x1
173 #define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
174 #define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
175 #define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
176 | (MUX_DPHY_SEL_SCLKMPLL << 8) \
177 | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
180 #define CORE_TIMERS_RATIO 0x1
181 #define COPY2_RATIO 0x3
182 #define DMCP_RATIO 0x1
183 #define DMCD_RATIO 0x1
184 #define DMC_RATIO 0x1
185 #define DPHY_RATIO 0x1
186 #define ACP_PCLK_RATIO 0x1
187 #define ACP_RATIO 0x3
188 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
189 | (COPY2_RATIO << 24) \
190 | (DMCP_RATIO << 20) \
191 | (DMCD_RATIO << 16) \
192 | (DMC_RATIO << 12) \
193 | (DPHY_RATIO << 8) \
194 | (ACP_PCLK_RATIO << 4) \
198 #define DPM_RATIO 0x1
199 #define DVSEM_RATIO 0x1
200 #define PWI_RATIO 0x1
201 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
202 | (DVSEM_RATIO << 16) \
206 #define MUX_ONENAND_SEL_ACLK_133 0x0
207 #define MUX_ONENAND_SEL_ACLK_160 0x1
208 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
209 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
210 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
211 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
212 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
213 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
214 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
215 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
216 #define MUX_VPLL_SEL_FINPLL 0x0
217 #define MUX_VPLL_SEL_FOUTVPLL 0x1
218 #define MUX_EPLL_SEL_FINPLL 0x0
219 #define MUX_EPLL_SEL_FOUTEPLL 0x1
220 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
221 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
222 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
223 | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
224 | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
225 | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
226 | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
227 | (MUX_VPLL_SEL_FINPLL << 8) \
228 | (MUX_EPLL_SEL_FINPLL << 4)\
229 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
232 #define VPLLSRC_SEL_FINPLL 0x0
233 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
234 #define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
237 #define ONENAND_RATIO 0x0
238 #define ACLK_133_RATIO 0x5
239 #define ACLK_160_RATIO 0x4
240 #define ACLK_100_RATIO 0x7
241 #define ACLK_200_RATIO 0x3
242 #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
243 | (ACLK_133_RATIO << 12)\
244 | (ACLK_160_RATIO << 8) \
245 | (ACLK_100_RATIO << 4) \
246 | (ACLK_200_RATIO << 0))
248 /* CLK_SRC_LEFTBUS */
249 #define MUX_GDL_SEL_SCLKMPLL 0x0
250 #define MUX_GDL_SEL_SCLKAPLL 0x1
251 #define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
253 /* CLK_DIV_LEFTBUS */
254 #define GPL_RATIO 0x1
255 #define GDL_RATIO 0x3
256 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
258 /* CLK_SRC_RIGHTBUS */
259 #define MUX_GDR_SEL_SCLKMPLL 0x0
260 #define MUX_GDR_SEL_SCLKAPLL 0x1
261 #define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
263 /* CLK_DIV_RIGHTBUS */
264 #define GPR_RATIO 0x1
265 #define GDR_RATIO 0x3
266 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
268 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
269 #define SATA_SEL_SCLKMPLL 0
270 #define SATA_SEL_SCLKAPLL 1
272 #define MMC_SEL_XXTI 0
273 #define MMC_SEL_XUSBXTI 1
274 #define MMC_SEL_SCLK_HDMI24M 2
275 #define MMC_SEL_SCLK_USBPHY0 3
276 #define MMC_SEL_SCLK_USBPHY1 4
277 #define MMC_SEL_SCLK_HDMIPHY 5
278 #define MMC_SEL_SCLKMPLL 6
279 #define MMC_SEL_SCLKEPLL 7
280 #define MMC_SEL_SCLKVPLL 8
282 #define MMCC0_SEL MMC_SEL_SCLKMPLL
283 #define MMCC1_SEL MMC_SEL_SCLKMPLL
284 #define MMCC2_SEL MMC_SEL_SCLKMPLL
285 #define MMCC3_SEL MMC_SEL_SCLKMPLL
286 #define MMCC4_SEL MMC_SEL_SCLKMPLL
287 #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
288 | (MMCC4_SEL << 16) \
289 | (MMCC3_SEL << 12) \
294 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
296 #define MMC0_RATIO 0xF
297 #define MMC0_PRE_RATIO 0x0
298 #define MMC1_RATIO 0xF
299 #define MMC1_PRE_RATIO 0x0
300 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
301 | (MMC1_RATIO << 16) \
302 | (MMC0_PRE_RATIO << 8) \
306 #define MMC2_RATIO 0xF
307 #define MMC2_PRE_RATIO 0x0
308 #define MMC3_RATIO 0xF
309 #define MMC3_PRE_RATIO 0x0
310 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
311 | (MMC3_RATIO << 16) \
312 | (MMC2_PRE_RATIO << 8) \
316 #define MMC4_RATIO 0xF
317 #define MMC4_PRE_RATIO 0x0
318 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
322 #define UART_SEL_XXTI 0
323 #define UART_SEL_XUSBXTI 1
324 #define UART_SEL_SCLK_HDMI24M 2
325 #define UART_SEL_SCLK_USBPHY0 3
326 #define UART_SEL_SCLK_USBPHY1 4
327 #define UART_SEL_SCLK_HDMIPHY 5
328 #define UART_SEL_SCLKMPLL 6
329 #define UART_SEL_SCLKEPLL 7
330 #define UART_SEL_SCLKVPLL 8
332 #define UART0_SEL UART_SEL_SCLKMPLL
333 #define UART1_SEL UART_SEL_SCLKMPLL
334 #define UART2_SEL UART_SEL_SCLKMPLL
335 #define UART3_SEL UART_SEL_SCLKMPLL
336 #define UART4_SEL UART_SEL_SCLKMPLL
337 #define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
338 | (UART3_SEL << 12) \
343 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
345 #define UART0_RATIO 7
346 #define UART1_RATIO 7
347 #define UART2_RATIO 7
348 #define UART3_RATIO 7
349 #define UART4_RATIO 7
350 #define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
351 | (UART3_RATIO << 12) \
352 | (UART2_RATIO << 8) \
353 | (UART1_RATIO << 4) \
354 | (UART0_RATIO << 0))
357 #define FIMD_SEL_SCLKMPLL 6
358 #define MDNIE0_SEL_XUSBXTI 1
359 #define MDNIE_PWM0_SEL_XUSBXTI 1
360 #define MIPI0_SEL_XUSBXTI 1
361 #define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
362 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
363 | (MDNIE0_SEL_XUSBXTI << 4) \
364 | (FIMD_SEL_SCLKMPLL << 0))
366 /* Required period to generate a stable clock output */
368 #define PLL_LOCKTIME 0x1C20
373 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
379 #define APLL_MDIV 0xFA
380 #define APLL_PDIV 0x6
381 #define APLL_SDIV 0x1
382 #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
385 #define APLL_AFC_ENB 0x1
387 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
390 #define MPLL_MDIV 0xC8
391 #define MPLL_PDIV 0x6
392 #define MPLL_SDIV 0x1
393 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
396 #define MPLL_AFC_ENB 0x0
397 #define MPLL_AFC 0x1C
398 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
401 #define EPLL_MDIV 0x30
402 #define EPLL_PDIV 0x3
403 #define EPLL_SDIV 0x2
404 #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
408 #define EPLL_CON1_VAL (EPLL_K >> 0)
411 #define VPLL_MDIV 0x35
412 #define VPLL_PDIV 0x3
413 #define VPLL_SDIV 0x2
414 #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
417 #define VPLL_SSCG_EN DISABLE
418 #define VPLL_SEL_PF_DN_SPREAD 0x0
419 #define VPLL_MRR 0x11
422 #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
423 | (VPLL_SEL_PF_DN_SPREAD << 29) \
428 * UART GPIO_A0/GPIO_A1 Control Register Value
431 #define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
432 #define EXYNOS4_GPIO_A1_CON_VAL 0x222222
434 /* ULCON: UART Line Control Value 8N1 */
435 #define WORD_LEN_5_BIT 0x00
436 #define WORD_LEN_6_BIT 0x01
437 #define WORD_LEN_7_BIT 0x02
438 #define WORD_LEN_8_BIT 0x03
440 #define STOP_BIT_1 0x00
441 #define STOP_BIT_2 0x01
443 #define NO_PARITY 0x00
444 #define ODD_PARITY 0x4
445 #define EVEN_PARITY 0x5
446 #define FORCED_PARITY_CHECK_AS_1 0x6
447 #define FORCED_PARITY_CHECK_AS_0 0x7
449 #define INFRAMODE_NORMAL 0x00
450 #define INFRAMODE_INFRARED 0x01
452 #define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
454 | (STOP_BIT_1 << 2) \
455 | (WORD_LEN_8_BIT << 0))
458 * UCON: UART Control Value
459 * Tx_interrupt Type: Level
460 * Rx_interrupt Type: Level
461 * Rx Timeout Enabled: Yes
462 * Rx-Error Atatus_Int Enable: Yes
465 * Transmit mode : Interrupt request/polling
466 * Receive mode : Interrupt request/polling
468 #define TX_PULSE_INTERRUPT 0
469 #define TX_LEVEL_INTERRUPT 1
470 #define RX_PULSE_INTERRUPT 0
471 #define RX_LEVEL_INTERRUPT 1
473 #define RX_TIME_OUT ENABLE
474 #define RX_ERROR_STATE_INT_ENB ENABLE
475 #define LOOP_BACK DISABLE
476 #define BREAK_SIGNAL DISABLE
478 #define TX_MODE_DISABLED 0X00
479 #define TX_MODE_IRQ_OR_POLL 0X01
480 #define TX_MODE_DMA 0X02
482 #define RX_MODE_DISABLED 0X00
483 #define RX_MODE_IRQ_OR_POLL 0X01
484 #define RX_MODE_DMA 0X02
486 #define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
487 | (RX_LEVEL_INTERRUPT << 8) \
488 | (RX_TIME_OUT << 7) \
489 | (RX_ERROR_STATE_INT_ENB << 6) \
491 | (BREAK_SIGNAL << 4) \
492 | (TX_MODE_IRQ_OR_POLL << 2) \
493 | (RX_MODE_IRQ_OR_POLL << 0))
496 * UFCON: UART FIFO Control Value
497 * Tx FIFO Trigger LEVEL: 2 Bytes (001)
498 * Rx FIFO Trigger LEVEL: 2 Bytes (001)
503 #define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
504 #define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
505 #define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
506 #define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
507 #define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
508 #define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
509 #define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
510 #define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
512 #define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
513 #define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
514 #define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
515 #define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
516 #define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
517 #define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
518 #define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
519 #define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
521 #define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
522 #define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
523 #define TX_FIFO_RESET DISABLE
524 #define RX_FIFO_RESET DISABLE
525 #define FIFO_ENABLE ENABLE
526 #define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
527 | (RX_FIFO_TRIGGER_LEVEL << 4) \
528 | (TX_FIFO_RESET << 2) \
529 | (RX_FIFO_RESET << 1) \
530 | (FIFO_ENABLE << 0))
532 * Baud Rate Division Value
534 * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
535 * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
537 #define UBRDIV_VAL 0x35
540 * Fractional Part of Baud Rate Divisor:
542 * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
543 * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
545 #define UFRACVAL_VAL 0x4
548 * TZPC Register Value :
549 * R0SIZE: 0x0 : Size of secured ram
554 * TZPC Decode Protection Register Value :
555 * DECPROTXSET: 0xFF : Set Decode region to non-secure
557 #define DECPROTXSET 0xFF