2 * Lowlevel setup for ORIGEN board based on EXYNOS4210
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/cpu.h>
28 #include "origen_setup.h"
33 * r7 has GPIO part1 base 0x11400000
34 * r6 has GPIO part2 base 0x11000000
38 .word CONFIG_SYS_TEXT_BASE
44 /* r5 has always zero */
46 ldr r7, =EXYNOS4_GPIO_PART1_BASE
47 ldr r6, =EXYNOS4_GPIO_PART2_BASE
49 /* check reset status */
50 ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
53 /* AFTR wakeup reset */
54 ldr r2, =S5P_CHECK_DIDLE
58 /* LPA wakeup reset */
59 ldr r2, =S5P_CHECK_LPA
63 /* Sleep wakeup reset */
64 ldr r2, =S5P_CHECK_SLEEP
69 * If U-boot is already running in ram, no need to relocate U-Boot.
70 * Memory controller must be configured before relocating U-Boot
73 ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
74 bic r1, pc, r0 /* pc <- current addr of code */
75 /* r1 <- unmasked bits of pc */
76 ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
77 bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
78 cmp r1, r2 /* compare r1, r2 */
79 beq 1f /* r0 == r1 then skip sdram init */
81 /* init system clock */
84 /* Memory initialize */
101 /* Load return address and jump to kernel */
102 ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
104 /* r1 = physical address of exynos4210_cpu_resume function */
113 * system_clock_init: Initialize core clock and bus clock.
114 * void system_clock_init(void)
118 ldr r0, =EXYNOS4_CLOCK_BASE
120 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
121 ldr r1, =CLK_SRC_CPU_VAL
122 ldr r2, =CLK_SRC_CPU_OFFSET
130 ldr r1, =CLK_SRC_TOP0_VAL
131 ldr r2, =CLK_SRC_TOP0_OFFSET
134 ldr r1, =CLK_SRC_TOP1_VAL
135 ldr r2, =CLK_SRC_TOP1_OFFSET
139 ldr r1, =CLK_SRC_DMC_VAL
140 ldr r2, =CLK_SRC_DMC_OFFSET
144 ldr r1, =CLK_SRC_LEFTBUS_VAL
145 ldr r2, =CLK_SRC_LEFTBUS_OFFSET
148 /*CLK_SRC_RIGHTBUS */
149 ldr r1, =CLK_SRC_RIGHTBUS_VAL
150 ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
153 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
154 ldr r1, =CLK_SRC_FSYS_VAL
155 ldr r2, =CLK_SRC_FSYS_OFFSET
159 ldr r1, =CLK_SRC_PERIL0_VAL
160 ldr r2, =CLK_SRC_PERIL0_OFFSET
164 ldr r1, =CLK_SRC_CAM_VAL
165 ldr r2, =CLK_SRC_CAM_OFFSET
169 ldr r1, =CLK_SRC_MFC_VAL
170 ldr r2, =CLK_SRC_MFC_OFFSET
174 ldr r1, =CLK_SRC_G3D_VAL
175 ldr r2, =CLK_SRC_G3D_OFFSET
179 ldr r1, =CLK_SRC_LCD0_VAL
180 ldr r2, =CLK_SRC_LCD0_OFFSET
189 ldr r1, =CLK_DIV_CPU0_VAL
190 ldr r2, =CLK_DIV_CPU0_OFFSET
194 ldr r1, =CLK_DIV_CPU1_VAL
195 ldr r2, =CLK_DIV_CPU1_OFFSET
199 ldr r1, =CLK_DIV_DMC0_VAL
200 ldr r2, =CLK_DIV_DMC0_OFFSET
204 ldr r1, =CLK_DIV_DMC1_VAL
205 ldr r2, =CLK_DIV_DMC1_OFFSET
208 /* CLK_DIV_LEFTBUS */
209 ldr r1, =CLK_DIV_LEFTBUS_VAL
210 ldr r2, =CLK_DIV_LEFTBUS_OFFSET
213 /* CLK_DIV_RIGHTBUS */
214 ldr r1, =CLK_DIV_RIGHTBUS_VAL
215 ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
219 ldr r1, =CLK_DIV_TOP_VAL
220 ldr r2, =CLK_DIV_TOP_OFFSET
224 ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
225 ldr r2, =CLK_DIV_FSYS1_OFFSET
229 ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
230 ldr r2, =CLK_DIV_FSYS2_OFFSET
234 ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
235 ldr r2, =CLK_DIV_FSYS3_OFFSET
238 /* CLK_DIV_PERIL0: UART Clock Divisors */
239 ldr r1, =CLK_DIV_PERIL0_VAL
240 ldr r2, =CLK_DIV_PERIL0_OFFSET
243 /* CAM, FIMC 0-3: CAM Clock Divisors */
244 ldr r1, =CLK_DIV_CAM_VAL
245 ldr r2, =CLK_DIV_CAM_OFFSET
248 /* CLK_DIV_MFC: MFC Clock Divisors */
249 ldr r1, =CLK_DIV_MFC_VAL
250 ldr r2, =CLK_DIV_MFC_OFFSET
253 /* CLK_DIV_G3D: G3D Clock Divisors */
254 ldr r1, =CLK_DIV_G3D_VAL
255 ldr r2, =CLK_DIV_G3D_OFFSET
258 /* CLK_DIV_LCD0: LCD0 Clock Divisors */
259 ldr r1, =CLK_DIV_LCD0_VAL
260 ldr r2, =CLK_DIV_LCD0_OFFSET
263 /* Set PLL locktime */
264 ldr r1, =PLL_LOCKTIME
265 ldr r2, =APLL_LOCK_OFFSET
268 ldr r1, =PLL_LOCKTIME
269 ldr r2, =MPLL_LOCK_OFFSET
272 ldr r1, =PLL_LOCKTIME
273 ldr r2, =EPLL_LOCK_OFFSET
276 ldr r1, =PLL_LOCKTIME
277 ldr r2, =VPLL_LOCK_OFFSET
281 ldr r1, =APLL_CON1_VAL
282 ldr r2, =APLL_CON1_OFFSET
286 ldr r1, =APLL_CON0_VAL
287 ldr r2, =APLL_CON0_OFFSET
291 ldr r1, =MPLL_CON1_VAL
292 ldr r2, =MPLL_CON1_OFFSET
296 ldr r1, =MPLL_CON0_VAL
297 ldr r2, =MPLL_CON0_OFFSET
301 ldr r1, =EPLL_CON1_VAL
302 ldr r2, =EPLL_CON1_OFFSET
306 ldr r1, =EPLL_CON0_VAL
307 ldr r2, =EPLL_CON0_OFFSET
311 ldr r1, =VPLL_CON1_VAL
312 ldr r2, =VPLL_CON1_OFFSET
316 ldr r1, =VPLL_CON0_VAL
317 ldr r2, =VPLL_CON0_OFFSET
327 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
328 * void uart_asm_init(void)
333 /* setup UART0-UART3 GPIOs (part1) */
335 ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
336 str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
337 ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
338 str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
340 ldr r0, =EXYNOS4_UART_BASE
341 add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
344 str r1, [r0, #ULCON_OFFSET]
346 str r1, [r0, #UCON_OFFSET]
348 str r1, [r0, #UFCON_OFFSET]
350 str r1, [r0, #UBRDIV_OFFSET]
351 ldr r1, =UFRACVAL_VAL
352 str r1, [r0, #UFRACVAL_OFFSET]