2 * Lowlevel setup for ORIGEN board based on EXYNOS4210
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/cpu.h>
28 #include "origen_setup.h"
33 * r7 has GPIO part1 base 0x11400000
34 * r6 has GPIO part2 base 0x11000000
38 .word CONFIG_SYS_TEXT_BASE
44 /* r5 has always zero */
46 ldr r7, =EXYNOS4_GPIO_PART1_BASE
47 ldr r6, =EXYNOS4_GPIO_PART2_BASE
49 /* check reset status */
50 ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
53 /* AFTR wakeup reset */
54 ldr r2, =S5P_CHECK_DIDLE
58 /* LPA wakeup reset */
59 ldr r2, =S5P_CHECK_LPA
63 /* Sleep wakeup reset */
64 ldr r2, =S5P_CHECK_SLEEP
69 * If U-boot is already running in ram, no need to relocate U-Boot.
70 * Memory controller must be configured before relocating U-Boot
73 ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
74 bic r1, pc, r0 /* pc <- current addr of code */
75 /* r1 <- unmasked bits of pc */
76 ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
77 bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
78 cmp r1, r2 /* compare r1, r2 */
79 beq 1f /* r0 == r1 then skip sdram init */
81 /* init system clock */
84 /* Memory initialize */
99 /* Load return address and jump to kernel */
100 ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
102 /* r1 = physical address of exynos4210_cpu_resume function */
111 * system_clock_init: Initialize core clock and bus clock.
112 * void system_clock_init(void)
116 ldr r0, =EXYNOS4_CLOCK_BASE
118 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
119 ldr r1, =CLK_SRC_CPU_VAL
120 ldr r2, =CLK_SRC_CPU_OFFSET
128 ldr r1, =CLK_SRC_TOP0_VAL
129 ldr r2, =CLK_SRC_TOP0_OFFSET
132 ldr r1, =CLK_SRC_TOP1_VAL
133 ldr r2, =CLK_SRC_TOP1_OFFSET
137 ldr r1, =CLK_SRC_DMC_VAL
138 ldr r2, =CLK_SRC_DMC_OFFSET
142 ldr r1, =CLK_SRC_LEFTBUS_VAL
143 ldr r2, =CLK_SRC_LEFTBUS_OFFSET
146 /*CLK_SRC_RIGHTBUS */
147 ldr r1, =CLK_SRC_RIGHTBUS_VAL
148 ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
151 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
152 ldr r1, =CLK_SRC_FSYS_VAL
153 ldr r2, =CLK_SRC_FSYS_OFFSET
157 ldr r1, =CLK_SRC_PERIL0_VAL
158 ldr r2, =CLK_SRC_PERIL0_OFFSET
162 ldr r1, =CLK_SRC_LCD0_VAL
163 ldr r2, =CLK_SRC_LCD0_OFFSET
172 ldr r1, =CLK_DIV_CPU0_VAL
173 ldr r2, =CLK_DIV_CPU0_OFFSET
177 ldr r1, =CLK_DIV_CPU1_VAL
178 ldr r2, =CLK_DIV_CPU1_OFFSET
182 ldr r1, =CLK_DIV_DMC0_VAL
183 ldr r2, =CLK_DIV_DMC0_OFFSET
187 ldr r1, =CLK_DIV_DMC1_VAL
188 ldr r2, =CLK_DIV_DMC1_OFFSET
191 /* CLK_DIV_LEFTBUS */
192 ldr r1, =CLK_DIV_LEFTBUS_VAL
193 ldr r2, =CLK_DIV_LEFTBUS_OFFSET
196 /* CLK_DIV_RIGHTBUS */
197 ldr r1, =CLK_DIV_RIGHTBUS_VAL
198 ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
202 ldr r1, =CLK_DIV_TOP_VAL
203 ldr r2, =CLK_DIV_TOP_OFFSET
207 ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
208 ldr r2, =CLK_DIV_FSYS1_OFFSET
212 ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
213 ldr r2, =CLK_DIV_FSYS2_OFFSET
217 ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
218 ldr r2, =CLK_DIV_FSYS3_OFFSET
221 /* CLK_DIV_PERIL0: UART Clock Divisors */
222 ldr r1, =CLK_DIV_PERIL0_VAL
223 ldr r2, =CLK_DIV_PERIL0_OFFSET
226 /* Set PLL locktime */
227 ldr r1, =PLL_LOCKTIME
228 ldr r2, =APLL_LOCK_OFFSET
231 ldr r1, =PLL_LOCKTIME
232 ldr r2, =MPLL_LOCK_OFFSET
235 ldr r1, =PLL_LOCKTIME
236 ldr r2, =EPLL_LOCK_OFFSET
239 ldr r1, =PLL_LOCKTIME
240 ldr r2, =VPLL_LOCK_OFFSET
244 ldr r1, =APLL_CON1_VAL
245 ldr r2, =APLL_CON1_OFFSET
249 ldr r1, =APLL_CON0_VAL
250 ldr r2, =APLL_CON0_OFFSET
254 ldr r1, =MPLL_CON1_VAL
255 ldr r2, =MPLL_CON1_OFFSET
259 ldr r1, =MPLL_CON0_VAL
260 ldr r2, =MPLL_CON0_OFFSET
264 ldr r1, =EPLL_CON1_VAL
265 ldr r2, =EPLL_CON1_OFFSET
269 ldr r1, =EPLL_CON0_VAL
270 ldr r2, =EPLL_CON0_OFFSET
274 ldr r1, =VPLL_CON1_VAL
275 ldr r2, =VPLL_CON1_OFFSET
279 ldr r1, =VPLL_CON0_VAL
280 ldr r2, =VPLL_CON0_OFFSET
290 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
291 * void uart_asm_init(void)
296 /* setup UART0-UART3 GPIOs (part1) */
298 ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
299 str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
300 ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
301 str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
303 ldr r0, =EXYNOS4_UART_BASE
304 add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
307 str r1, [r0, #ULCON_OFFSET]
309 str r1, [r0, #UCON_OFFSET]
311 str r1, [r0, #UFCON_OFFSET]
313 str r1, [r0, #UBRDIV_OFFSET]
314 ldr r1, =UFRACVAL_VAL
315 str r1, [r0, #UFRACVAL_OFFSET]
321 /* Setting TZPC[TrustZone Protection Controller] */
327 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
328 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
329 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
330 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
333 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
334 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
335 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
336 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
339 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
340 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
341 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
342 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
345 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
346 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
347 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
348 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
351 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
352 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
353 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
354 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
357 str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
358 str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
359 str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
360 str r1, [r0, #TZPC_DECPROT3SET_OFFSET]