2 * Copyright (C) 2009 Samsung Electrnoics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 .globl mem_ctrl_asm_init
15 ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
16 ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
17 ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
19 /* DLL parameter setting */
21 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
22 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
24 str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
25 strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
27 streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
31 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
32 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
36 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
37 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
40 wait: subs r2, r2, #0x1
45 /* Force value locking for DLL off */
46 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
47 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
51 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
52 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
54 /* auto refresh off */
55 ldr r1, =0xff001010 | (1 << 7)
56 ldr r2, =0xff001010 | (1 << 7)
57 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
58 strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
61 * Burst Length 4, 2 chips, 32-bit, LPDDR
62 * OFF: dynamic self refresh, force precharge, dynamic power down off
66 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
67 strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
71 * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
72 * So finally Bank1 OneDRAM should address start at at 0x3000'0000
76 * DMC0: CS0 : S5PC100/S5PC110
87 str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
88 str r4, [r0, #0x00C] @ dummy write
93 * 0xf8 -> 0x47FFFFFF (1Gib)
95 * 0xf0 -> 0x4FFFFFFF (2Gib)
97 * [11:8 ] 2: 9 bits - Col (1Gib)
98 * [11:8 ] 3: 10 bits - Col (2Gib)
99 * [ 7:4 ] 2: 14 bits - Row
103 ldr r4, =0x40f01322 @ 2Gib: MCP B
104 ldr r5, =0x50f81312 @ dummy: MCP D
106 ldreq r4, =0x40f81222 @ 1Gib: MCP A
108 ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
110 ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
113 strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
114 strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
125 eoreq r3, r3, #0x08000000
126 streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
129 str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
130 strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
131 strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
141 * 7.8us * 200MHz %LE %LONG1560(0x618)
142 * 7.8us * 166MHz %LE %LONG1294(0x50E)
143 * 7.8us * 133MHz %LE %LONG1038(0x40E),
144 * 7.8us * 100MHz %LE %LONG780(0x30C),
147 str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
148 ldrne r1, =0x00000618
149 strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
152 str r1, [r0, #0x034] @ TIMINGROW_OFFSET
153 ldrne r1, =0x182332c8
154 strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
157 str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
158 ldrne r1, =0x13130005
159 strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
162 str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
163 ldrne r1, =0x0E180222
164 strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
168 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
169 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
173 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
174 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
178 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
179 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
181 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
182 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
186 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
187 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
191 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
192 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
196 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
197 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
201 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
202 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
206 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
207 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
209 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
210 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
214 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
215 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
219 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
220 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
222 /* auto refresh on */
223 ldr r1, =0xFF002030 | (1 << 7)
224 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
225 strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
229 str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
230 strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
233 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
234 strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
236 /* Skip when S5PC110 */
239 /* Check OneDRAM access area at s5pc100 */
240 ldreq r3, =0x38f80222
241 ldreq r1, =0x37ffff00