2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/power.h>
20 * r7 has S5PC100 GPIO base, 0xE0300000
21 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
22 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
26 .word CONFIG_SYS_TEXT_BASE
32 /* r5 has always zero */
35 ldr r7, =S5PC100_GPIO_BASE
36 ldr r8, =S5PC100_GPIO_BASE
38 ldr r2, =S5PC110_PRO_ID
44 ldr r8, =S5PC110_GPIO_BASE
46 /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
48 beq skip_check_didle @ Support C110 only
50 ldr r0, =S5PC110_RST_STAT
52 and r1, r1, #0x000D0000
53 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
58 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
59 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
60 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
61 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
62 orr r1, r1, #(0x1 << 4)
63 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
65 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
67 str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
69 /* Don't setup at s5pc100 */
73 * Initialize Async Register Setting for EVT1
74 * Because we are setting EVT1 as the default value of EVT0,
75 * setting EVT0 as well does not make things worse.
76 * Thus, for the simplicity, we set for EVT0, too
78 * The "Async Registers" are:
147 * Diable ABB block to reduce sleep current at low temperature
148 * Note that it's hidden register setup don't modify it
155 /* IO retension release */
156 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
157 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
159 ldreq r2, =(1 << 31) @ IO_RET_REL
160 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
162 /* Do not release retention here for S5PC110 */
165 /* Disable Watchdog */
166 ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
167 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
171 ldreq r0, =S5PC100_SROMC_BASE
172 ldrne r0, =S5PC110_SROMC_BASE
176 /* S5PC100 has 3 groups of interrupt sources */
177 ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
178 ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
179 add r1, r0, #0x00100000
180 add r2, r0, #0x00200000
182 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
184 str r3, [r0, #0x14] @ INTENCLEAR
185 str r3, [r1, #0x14] @ INTENCLEAR
186 str r3, [r2, #0x14] @ INTENCLEAR
188 /* Set all interrupts as IRQ */
189 str r5, [r0, #0xc] @ INTSELECT
190 str r5, [r1, #0xc] @ INTSELECT
191 str r5, [r2, #0xc] @ INTSELECT
193 /* Pending Interrupt Clear */
194 str r5, [r0, #0xf00] @ INTADDRESS
195 str r5, [r1, #0xf00] @ INTADDRESS
196 str r5, [r2, #0xf00] @ INTADDRESS
204 /* Clear wakeup status register */
205 ldreq r0, =S5PC100_WAKEUP_STAT
206 ldrne r0, =S5PC110_WAKEUP_STAT
210 /* IO retension release */
211 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
212 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
214 ldreq r2, =(1 << 31) @ IO_RET_REL
215 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
222 /* Wait when APLL is locked */
223 ldr r0, =0xE0100100 @ S5PC110_APLL_CON
226 and r1, r1, #(1 << 29)
230 ldr r0, =S5PC110_INFORM0
244 * system_clock_init: Initialize core clock and bus clock.
245 * void system_clock_init(void)
248 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
255 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
256 str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
257 str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
258 str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
259 str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
262 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
265 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
268 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
271 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
288 /* Set Source Clock */
289 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
290 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
294 ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
296 /* Set OSC_FREQ value */
298 str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
300 /* Set MTC_STABLE value */
302 str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
304 /* Set CLAMP_STABLE value */
306 str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
308 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
310 /* Set Clock divider */
311 ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
313 ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
317 ldr r1, =0x2cf @ Locktime : 30us
318 str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
319 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
320 str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
321 str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
322 str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
324 /* S5PC110_APLL_CON */
325 ldr r1, =0x80C80601 @ 800MHz
327 /* S5PC110_MPLL_CON */
328 ldr r1, =0x829B0C01 @ 667MHz
330 /* S5PC110_EPLL_CON */
331 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
333 /* S5PC110_VPLL_CON */
334 ldr r1, =0x806C0603 @ 54MHz
337 /* Set Source Clock */
338 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
339 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
341 /* OneDRAM(DMC0) clock setting */
342 ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
343 str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
344 ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
345 str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
347 /* XCLKOUT = XUSBXTI 24MHz */
348 add r2, r0, #0xE000 @ S5PC110_OTHERS
350 orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
354 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
355 str r1, [r0, #0x460] @ S5PC110_CLK_IP0
358 ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
360 str r1, [r0, #0x464] @ S5PC110_CLK_IP1
363 ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
364 @ HOSTIF[10] HSMMC0[16]
365 @ HSMMC2[18] VIC[27:24]
366 str r1, [r0, #0x468] @ S5PC110_CLK_IP2
369 ldr r1, =0x8eff038c @ I2C[8:6]
370 @ SYSTIMER[16] UART0[17]
371 @ UART1[18] UART2[19]
373 @ PWM[23] GPIO[26] SYSCON[27]
374 str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
377 ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
378 str r1, [r0, #0x470] @ S5PC110_CLK_IP3
381 /* wait at least 200us to stablize all clock */
389 ldreq r0, =0xE3800000
390 ldrne r0, =0xF1500000
397 * uart_asm_init: Initialize UART's pins
400 /* set GPIO to enable UART0-UART4 */
403 str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
405 str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
411 /* UART_SEL GPK0[5] at S5PC100 */
412 add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
413 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
414 bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
415 orr r1, r1, #(0x1 << 20) @ Output
416 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
418 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
419 bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
420 orr r1, r1, #(0x2 << 10) @ Pull-up enabled
421 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
423 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
424 orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
425 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
430 * Note that the following address
431 * 0xE020'0360 is reserved address at S5PC100
433 /* UART_SEL MP0_5[7] at S5PC110 */
434 add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
435 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
436 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
437 orr r1, r1, #(0x1 << 28) @ Output
438 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
440 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
441 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
442 orr r1, r1, #(0x2 << 14) @ Pull-up enabled
443 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
445 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
446 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
447 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET