3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Gerald Van Baren <vanbaren@cideas.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/u-boot.h>
33 #ifdef CONFIG_SHOW_BOOT_PROGRESS
34 #include <status_led.h>
37 #ifdef CONFIG_ETHER_LOOPBACK_TEST
38 extern void eth_loopback_test(void);
39 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
42 #include "ioconfig.h" /* I/O configuration table */
45 * PBI Page Based Interleaving
46 * PSDMR_PBI page based interleaving
47 * 0 bank based interleaving
48 * External Address Multiplexing (EAMUX) adds a clock to address cycles
49 * (this can help with marginal board layouts)
50 * PSDMR_EAMUX adds a clock
52 * Buffer Command (BUFCMD) adds a clock to command cycles.
53 * PSDMR_BUFCMD adds a clock
56 #define CONFIG_PBI PSDMR_PBI
57 #define PESSIMISTIC_SDRAM 0
58 #define EAMUX 0 /* EST requires EAMUX */
64 #define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
65 #define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
66 #define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
67 #define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
68 #define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
73 #define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
74 #define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
76 #define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
77 #define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
79 #define ADC_VREF_CAP 100 /* VREF capacitor in uF */
80 #define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
81 #define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
82 #define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
83 /* Wait at least 4100 LRCLK's */
85 #define ADC_REG1_FRAME_START 0x80 /* Frame start */
86 #define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
87 #define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
88 #define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
90 #define ADC_REG2_128x 0x80 /* Oversample at 128x */
91 #define ADC_REG2_CAL 0x40 /* System calibration enable */
92 #define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
93 #define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
94 #define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
95 #define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
96 #define ADC_REG2_DFS 0x02 /* Digital format select */
97 #define ADC_REG2_MUTE 0x01 /* Mute */
99 #define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
100 #define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
101 #define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
102 #define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
103 #define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
104 #define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
105 #define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
111 #define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
113 #define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
114 #define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
115 #define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
117 #define DAC_REG1_AMUTE 0x80 /* Auto-mute */
119 #define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
120 #define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
121 #define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
122 #define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
123 #define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
124 #define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
126 #define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
127 #define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
128 #define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
129 #define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
131 #define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
132 #define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
133 #define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
134 #define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
136 #define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
137 #define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
138 #define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
139 #define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
140 #define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
141 #define DAC_REG5_FREEZE 0x04 /* Freeze */
142 #define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
143 #define DAC_REG5_RESERVED 0x01 /* Reserved */
145 /* ------------------------------------------------------------------------- */
148 * Check Board Identity:
158 /* ------------------------------------------------------------------------- */
160 phys_size_t initdram(int board_type)
162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
163 volatile memctl8260_t *memctl = &immap->im_memctl;
164 volatile uchar c = 0;
165 volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
166 uint psdmr = CONFIG_SYS_PSDMR;
168 uint psrt = 14; /* for no SPD */
169 uint chipselects = 1; /* for no SPD */
170 uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
171 uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
172 #ifdef SDRAM_SPD_ADDR
189 #ifdef SDRAM_SPD_ADDR
190 /* Keep the compiler from complaining about potentially uninitialized vars */
191 data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
194 * Read the SDRAM SPD EEPROM via I2C.
196 i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
199 for(j = 1; j < 64; j++) { /* read only the checksummed bytes */
200 /* note: the I2C address autoincrements when alen == 0 */
201 i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
202 if(j == 5) chipselects = data & 0x0F;
203 else if(j == 6) data_width = data;
204 else if(j == 7) data_width |= data << 8;
205 else if(j == 3) rows = data & 0x0F;
206 else if(j == 4) cols = data & 0x0F;
209 * Refresh rate: this assumes the prescaler is set to
210 * approximately 1uSec per tick.
212 switch(data & 0x7F) {
214 case 0: psrt = 14 ; /* 15.625uS */ break;
215 case 1: psrt = 2; /* 3.9uS */ break;
216 case 2: psrt = 6; /* 7.8uS */ break;
217 case 3: psrt = 29; /* 31.3uS */ break;
218 case 4: psrt = 60; /* 62.5uS */ break;
219 case 5: psrt = 120; /* 125uS */ break;
222 else if(j == 17) banks = data;
224 caslatency = 3; /* default CL */
225 #if(PESSIMISTIC_SDRAM)
226 if((data & 0x04) != 0) caslatency = 3;
227 else if((data & 0x02) != 0) caslatency = 2;
228 else if((data & 0x01) != 0) caslatency = 1;
230 if((data & 0x01) != 0) caslatency = 1;
231 else if((data & 0x02) != 0) caslatency = 2;
232 else if((data & 0x04) != 0) caslatency = 3;
235 printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
241 printf ("WARNING: Configuration data checksum failure:"
242 " is 0x%02x, calculated 0x%02x\n",
249 /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
251 printf("WARNING: CL was %d, forcing to 2\n", caslatency);
255 printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
259 printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
263 if((data_width != 64) && (data_width != 72))
265 printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
268 width = 3; /* 2^3 = 8 bytes = 64 bits wide */
270 * Convert banks into log2(banks)
272 if (banks == 2) banks = 1;
273 else if(banks == 4) banks = 2;
274 else if(banks == 8) banks = 3;
276 sdram_size = 1 << (rows + cols + banks + width);
278 #if(CONFIG_PBI == 0) /* bank-based interleaving */
279 rowst = ((32 - 6) - (rows + cols + width)) * 2;
281 rowst = 32 - (rows + banks + cols + width);
284 or = ~(sdram_size - 1) | /* SDAM address mask */
285 ((banks-1) << 13) | /* banks per device */
286 (rowst << 9) | /* rowst */
287 ((rows - 9) << 6); /* numr */
289 memctl->memc_or2 = or;
292 * SDAM specifies the number of columns that are multiplexed
293 * (reference AN2165/D), defined to be (columns - 6) for page
294 * interleave, (columns - 8) for bank interleave.
296 * BSMA is 14 - max(rows, cols). The bank select lines come
297 * into play above the highest "address" line going into the
300 #if(CONFIG_PBI == 0) /* bank-based interleaving */
302 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
306 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
309 #if(PESSIMISTIC_SDRAM)
310 psdmr = (CONFIG_PBI |\
319 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
324 psdmr = (CONFIG_PBI |\
327 PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
328 PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
329 PSDMR_WRC_1C | /* 1 clock + 7nSec */
333 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
341 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
343 * "At system reset, initialization software must set up the
344 * programmable parameters in the memory controller banks registers
345 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
346 * system software should execute the following initialization sequence
347 * for each SDRAM device.
349 * 1. Issue a PRECHARGE-ALL-BANKS command
350 * 2. Issue eight CBR REFRESH commands
351 * 3. Issue a MODE-SET command to initialize the mode register
353 * Quote from Micron MT48LC8M16A2 data sheet:
355 * "...the SDRAM requires a 100uS delay prior to issuing any
356 * command other than a COMMAND INHIBIT or NOP. Starting at some
357 * point during this 100uS period and continuing at least through
358 * the end of this period, COMMAND INHIBIT or NOP commands should
361 * "Once the 100uS delay has been satisfied with at least one COMMAND
362 * INHIBIT or NOP command having been applied, a /PRECHARGE command/
363 * should be applied. All banks must then be precharged, thereby
364 * placing the device in the all banks idle state."
366 * "Once in the idle state, /two/ AUTO REFRESH cycles must be
367 * performed. After the AUTO REFRESH cycles are complete, the
368 * SDRAM is ready for mode register programming."
370 * (/emphasis/ mine, gvb)
372 * The way I interpret this, Micron start up sequence is:
373 * 1. Issue a PRECHARGE-BANK command (initial precharge)
374 * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
375 * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
376 * 4. Issue a MODE-SET command to initialize the mode register
380 * The initial commands are executed by setting P/LSDMR[OP] and
381 * accessing the SDRAM with a single-byte transaction."
383 * The appropriate BRx/ORx registers have already been set when we
384 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
387 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
388 memctl->memc_psrt = psrt;
390 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
393 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
394 for (i = 0; i < 8; i++)
397 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
400 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
404 * Do it a second time for the second set of chips if the DIMM has
405 * two chip selects (double sided).
407 if(chipselects > 1) {
408 ramaddr += sdram_size;
410 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
411 memctl->memc_or3 = or;
413 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
416 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
417 for (i = 0; i < 8; i++)
420 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
423 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
427 /* return total ram size */
428 return (sdram_size * chipselects);
431 /*-----------------------------------------------------------------------
432 * Board Control Functions
434 void board_poweroff (void)
436 while (1); /* hang forever */
440 #ifdef CONFIG_MISC_INIT_R
441 /* ------------------------------------------------------------------------- */
442 int misc_init_r(void)
445 * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
447 volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
448 volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
450 int reg; /* I2C register value */
451 char *ep; /* Environment pointer */
452 char str_buf[12] ; /* sprintf output buffer */
453 int sample_rate; /* ADC/DAC sample rate */
454 int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
455 int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
456 int right_just; /* Is the data to the DAC right justified? */
457 int mclk_divide; /* MCLK Divide */
458 int quiet; /* Quiet or minimal output mode */
461 if ((ep = getenv("quiet")) != NULL) {
462 quiet = simple_strtol(ep, NULL, 10);
465 setenv("quiet", "0");
469 * SACSng custom initialization:
470 * Start the ADC and DAC clocks, since the Crystal parts do not
471 * work on the I2C bus until the clocks are running.
474 sample_rate = INITIAL_SAMPLE_RATE;
475 if ((ep = getenv("DaqSampleRate")) != NULL) {
476 sample_rate = simple_strtol(ep, NULL, 10);
479 sample_64x = INITIAL_SAMPLE_64X;
480 sample_128x = INITIAL_SAMPLE_128X;
481 if ((ep = getenv("Daq64xSampling")) != NULL) {
482 sample_64x = simple_strtol(ep, NULL, 10);
491 if ((ep = getenv("Daq128xSampling")) != NULL) {
492 sample_128x = simple_strtol(ep, NULL, 10);
503 * Stop the clocks and wait for at least 1 LRCLK period
504 * to make sure the clocking has really stopped.
507 udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
510 * Initialize the clocks with the new rates
512 Daq_Init_Clocks(sample_rate, sample_64x);
513 sample_rate = Daq_Get_SampleRate();
516 * Start the clocks and wait for at least 1 LRCLK period
517 * to make sure the clocking has become stable.
519 Daq_Start_Clocks(sample_rate);
520 udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
522 sprintf(str_buf, "%d", sample_rate);
523 setenv("DaqSampleRate", str_buf);
526 setenv("Daq64xSampling", "1");
527 setenv("Daq128xSampling", NULL);
530 setenv("Daq64xSampling", NULL);
531 setenv("Daq128xSampling", "1");
535 * Display the ADC/DAC clocking information
538 Daq_Display_Clocks();
542 * Determine the DAC data justification
545 right_just = INITIAL_RIGHT_JUST;
546 if ((ep = getenv("DaqDACRightJustified")) != NULL) {
547 right_just = simple_strtol(ep, NULL, 10);
550 sprintf(str_buf, "%d", right_just);
551 setenv("DaqDACRightJustified", str_buf);
554 * Determine the DAC MCLK Divide
557 mclk_divide = INITIAL_MCLK_DIVIDE;
558 if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
559 mclk_divide = simple_strtol(ep, NULL, 10);
562 sprintf(str_buf, "%d", mclk_divide);
563 setenv("DaqDACMClockDivide", str_buf);
566 * Initializing the I2C address in the Crystal A/Ds:
568 * 1) Wait for VREF cap to settle (10uSec per uF)
569 * 2) Release pullup on SDATA
570 * 3) Write the I2C address to register 6
571 * 4) Enable address matching by setting the MSB in register 7
575 printf("Initializing the ADC...\n");
577 udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
579 iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
580 udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
582 i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
583 i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
584 ADC_REG7_ADDR_ENABLE);
586 i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
587 (sample_64x ? 0 : ADC_REG2_128x) |
588 ADC_REG2_HIGH_PASS_DIS |
589 ADC_REG2_SLAVE_MODE);
591 reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
592 if(reg != I2C_ADC_1_ADDR)
593 printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
594 reg, I2C_ADC_1_ADDR);
596 iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
597 udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
599 i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
601 i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
602 (sample_64x ? 0 : ADC_REG2_128x) |
603 ADC_REG2_HIGH_PASS_DIS |
604 ADC_REG2_SLAVE_MODE);
606 reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
607 if(reg != I2C_ADC_2_ADDR)
608 printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
609 reg, I2C_ADC_2_ADDR);
611 i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
612 ADC_REG1_FRAME_START |
613 ADC_REG1_GROUND_CAL);
615 i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
616 (sample_64x ? 0 : ADC_REG2_128x) |
618 ADC_REG2_HIGH_PASS_DIS |
619 ADC_REG2_SLAVE_MODE);
621 udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
622 i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
625 * Now that we have synchronized the ADC's, enable address
626 * selection on the second ADC as well as the first.
628 i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
631 * Initialize the Crystal DAC
633 * Two of the config lines are used for I2C so we have to set them
634 * to the proper initialization state without inadvertantly
635 * sending an I2C "start" sequence. When we bring the I2C back to
636 * the normal state, we send an I2C "stop" sequence.
639 printf("Initializing the DAC...\n");
643 * Bring the I2C clock and data lines low for initialization
652 iopa->pdat &= ~DAC_RST_MASK;
653 udelay(DAC_RESET_DELAY);
655 /* Release the DAC reset */
656 iopa->pdat |= DAC_RST_MASK;
657 udelay(DAC_INITIAL_DELAY);
661 * Enable control port (I2C mode)
662 * Going into power down
664 i2c_reg_write(I2C_DAC_ADDR, 0x05,
666 DAC_REG5_POWER_DOWN);
670 * Enable control port (I2C mode)
671 * Going into power down
675 i2c_reg_write(I2C_DAC_ADDR, 0x05,
677 DAC_REG5_POWER_DOWN |
678 (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
683 * . Format 0, left justified 24 bits
684 * . Format 3, right justified 24 bits
686 * . Single speed mode
687 * . Double speed mode
689 i2c_reg_write(I2C_DAC_ADDR, 0x01,
690 (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
691 DAC_REG1_LEFT_JUST_24_BIT) |
693 (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
695 sprintf(str_buf, "%d",
696 sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
697 setenv("DaqDACFunctionalMode", str_buf);
701 * Enable control port (I2C mode)
706 i2c_reg_write(I2C_DAC_ADDR, 0x05,
708 (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
711 * Create a I2C stop condition:
712 * low->high on data while clock is high.
724 #ifdef CONFIG_ETHER_LOOPBACK_TEST
726 * Run the Ethernet loopback test
728 eth_loopback_test ();
729 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
731 #ifdef CONFIG_SHOW_BOOT_PROGRESS
733 * Turn off the RED fail LED now that we are up and running.
735 status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
741 #ifdef CONFIG_SHOW_BOOT_PROGRESS
743 * Show boot status: flash the LED if something goes wrong, indicating
744 * that last thing that worked and thus, by implication, what is broken.
746 * This stores the last OK value in RAM so this will not work properly
747 * before RAM is initialized. Since it is being used for indicating
748 * boot status (i.e. after RAM is initialized), that is OK.
750 static void flash_code(uchar number, uchar modulo, uchar digits)
755 * Recursively do upper digits.
758 flash_code(number / modulo, modulo, digits - 1);
761 number = number % modulo;
764 * Zero is indicated by one long flash (dash).
767 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
769 status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
773 * Non-zero is indicated by short flashes, one per count.
775 for(j = 0; j < number; j++) {
776 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
778 status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
783 * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
788 static int last_boot_progress;
790 void show_boot_progress (int status)
794 last_boot_progress = status;
797 * If a specific failure code is given, flash this code
798 * else just use the last success code we've seen
801 last_boot_progress = -status;
804 * Flash this code 5 times
808 * Houston, we have a problem.
809 * Blink the last OK status which indicates where things failed.
811 status_led_set(STATUS_LED_RED, STATUS_LED_ON);
812 flash_code(last_boot_progress, 5, 3);
815 * Delay 5 seconds between repetitions,
816 * with the fault LED blinking
819 status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
821 status_led_set(STATUS_LED_RED, STATUS_LED_ON);
827 * Reset the board to retry initialization.
829 do_reset (NULL, 0, 0, NULL);
832 #endif /* CONFIG_SHOW_BOOT_PROGRESS */
836 * The following are used to control the SPI chip selects for the SPI command.
838 #if defined(CONFIG_CMD_SPI)
840 #define SPI_ADC_CS_MASK 0x00000800
841 #define SPI_DAC_CS_MASK 0x00001000
843 static const u32 cs_mask[] = {
848 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
850 return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
853 void spi_cs_activate(struct spi_slave *slave)
855 volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
857 iopd->pdat &= ~cs_mask[slave->cs];
860 void spi_cs_deactivate(struct spi_slave *slave)
862 volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
864 iopd->pdat |= cs_mask[slave->cs];
869 #endif /* CONFIG_MISC_INIT_R */