3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Jon Diekema <diekema@cideas.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/cpm_8260.h>
13 #include <configs/sacsng.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int Daq64xSampling = 0;
22 void Daq_BRG_Reset(uint brg)
24 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
25 volatile uint *brg_ptr;
27 brg_ptr = (uint *)&immr->im_brgc1;
30 brg_ptr = (uint *)&immr->im_brgc5;
34 *brg_ptr |= CPM_BRG_RST;
35 *brg_ptr &= ~CPM_BRG_RST;
38 void Daq_BRG_Disable(uint brg)
40 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
41 volatile uint *brg_ptr;
43 brg_ptr = (uint *)&immr->im_brgc1;
46 brg_ptr = (uint *)&immr->im_brgc5;
50 *brg_ptr &= ~CPM_BRG_EN;
53 void Daq_BRG_Enable(uint brg)
55 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
56 volatile uint *brg_ptr;
58 brg_ptr = (uint *)&immr->im_brgc1;
60 brg_ptr = (uint *)&immr->im_brgc5;
64 *brg_ptr |= CPM_BRG_EN;
67 uint Daq_BRG_Get_Div16(uint brg)
69 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
72 brg_ptr = (uint *)&immr->im_brgc1;
74 brg_ptr = (uint *)&immr->im_brgc5;
79 if (*brg_ptr & CPM_BRG_DIV16) {
89 void Daq_BRG_Set_Div16(uint brg, uint div16)
91 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
94 brg_ptr = (uint *)&immr->im_brgc1;
96 brg_ptr = (uint *)&immr->im_brgc5;
103 *brg_ptr |= CPM_BRG_DIV16;
107 *brg_ptr &= ~CPM_BRG_DIV16;
111 uint Daq_BRG_Get_Count(uint brg)
113 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
117 brg_ptr = (uint *)&immr->im_brgc1;
119 brg_ptr = (uint *)&immr->im_brgc5;
124 /* Get the clock divider
126 * Note: A clock divider of 0 means divide by 1,
127 * therefore we need to add 1 to the count.
129 brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
131 if (*brg_ptr & CPM_BRG_DIV16) {
138 void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
140 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
143 brg_ptr = (uint *)&immr->im_brgc1;
145 brg_ptr = (uint *)&immr->im_brgc5;
151 * Note: A clock divider of 0 means divide by 1,
152 * therefore we need to subtract 1 from the count.
154 if (brg_cnt > 4096) {
155 /* Prescale = Divide by 16 */
156 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
157 (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
158 *brg_ptr |= CPM_BRG_DIV16;
161 /* Prescale = Divide by 1 */
162 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
163 ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
164 *brg_ptr &= ~CPM_BRG_DIV16;
168 uint Daq_BRG_Get_ExtClk(uint brg)
170 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
173 brg_ptr = (uint *)&immr->im_brgc1;
175 brg_ptr = (uint *)&immr->im_brgc5;
180 return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
183 char* Daq_BRG_Get_ExtClk_Description(uint brg)
187 extc = Daq_BRG_Get_ExtClk(brg);
228 void Daq_BRG_Set_ExtClk(uint brg, uint extc)
230 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
233 brg_ptr = (uint *)&immr->im_brgc1;
235 brg_ptr = (uint *)&immr->im_brgc5;
240 *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
241 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
244 uint Daq_BRG_Rate(uint brg)
246 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
251 brg_ptr = (uint *)&immr->im_brgc1;
254 brg_ptr = (uint *)&immr->im_brgc5;
255 brg_ptr += (brg - 4);
258 brg_cnt = Daq_BRG_Get_Count(brg);
260 switch (Daq_BRG_Get_ExtClk(brg)) {
261 case CPM_BRG_EXTC_CLK3:
262 case CPM_BRG_EXTC_CLK5: {
267 brg_freq = (uint)BRG_INT_CLK / brg_cnt;
273 uint Daq_Get_SampleRate(void)
276 * Read the BRG's to return the actual sample rate.
278 return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
281 void Daq_Init_Clocks(int sample_rate, int sample_64x)
283 volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
284 uint mclk_divisor; /* MCLK divisor */
285 int flag; /* Interrupt state */
287 /* Save off the clocking data */
288 Daq64xSampling = sample_64x;
291 * Limit the sample rate to some sensible values.
293 if (sample_rate > MAX_64x_SAMPLE_RATE) {
294 sample_rate = MAX_64x_SAMPLE_RATE;
296 if (sample_rate < MIN_SAMPLE_RATE) {
297 sample_rate = MIN_SAMPLE_RATE;
301 * Initialize the MCLK/SCLK/LRCLK baud rate generators.
305 Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
308 # ifdef RUN_SCLK_ON_BRG_INT
309 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
311 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
315 # ifdef RUN_LRCLK_ON_BRG_INT
316 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
318 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
322 * Dynamically adjust MCLK based on the new sample rate.
325 /* Compute the divisors */
326 mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
329 * Disable interrupt and save the current state
331 flag = disable_interrupts();
334 Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
337 # ifdef RUN_SCLK_ON_BRG_INT
338 Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
340 Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
343 # ifdef RUN_LRCLK_ON_BRG_INT
344 Daq_BRG_Set_Count(LRCLK_BRG,
345 mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
347 Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
351 * Restore the Interrupt state
357 /* Enable the clock drivers */
358 iopa->pdat &= ~SLRCLK_EN_MASK;
361 void Daq_Stop_Clocks(void)
364 #ifdef TIGHTEN_UP_BRG_TIMING
365 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
366 register uint mclk_brg; /* MCLK BRG value */
367 register uint sclk_brg; /* SCLK BRG value */
368 register uint lrclk_brg; /* LRCLK BRG value */
369 unsigned long flag; /* Interrupt flags */
372 # ifdef TIGHTEN_UP_BRG_TIMING
374 * Obtain MCLK BRG reset/disabled value
377 mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
380 mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
383 mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
386 mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
389 mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
392 mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
395 mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
398 mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
402 * Obtain SCLK BRG reset/disabled value
405 sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
408 sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
411 sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
414 sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
417 sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
420 sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
423 sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
426 sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
430 * Obtain LRCLK BRG reset/disabled value
432 # if (LRCLK_BRG == 0)
433 lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
435 # if (LRCLK_BRG == 1)
436 lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
438 # if (LRCLK_BRG == 2)
439 lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
441 # if (LRCLK_BRG == 3)
442 lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
444 # if (LRCLK_BRG == 4)
445 lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
447 # if (LRCLK_BRG == 5)
448 lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
450 # if (LRCLK_BRG == 6)
451 lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
453 # if (LRCLK_BRG == 7)
454 lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
458 * Disable interrupt and save the current state
460 flag = disable_interrupts();
463 * Set reset on MCLK BRG
466 *IM_BRGC1 = mclk_brg;
469 *IM_BRGC2 = mclk_brg;
472 *IM_BRGC3 = mclk_brg;
475 *IM_BRGC4 = mclk_brg;
478 *IM_BRGC5 = mclk_brg;
481 *IM_BRGC6 = mclk_brg;
484 *IM_BRGC7 = mclk_brg;
487 *IM_BRGC8 = mclk_brg;
491 * Set reset on SCLK BRG
494 *IM_BRGC1 = sclk_brg;
497 *IM_BRGC2 = sclk_brg;
500 *IM_BRGC3 = sclk_brg;
503 *IM_BRGC4 = sclk_brg;
506 *IM_BRGC5 = sclk_brg;
509 *IM_BRGC6 = sclk_brg;
512 *IM_BRGC7 = sclk_brg;
515 *IM_BRGC8 = sclk_brg;
519 * Set reset on LRCLK BRG
521 # if (LRCLK_BRG == 0)
522 *IM_BRGC1 = lrclk_brg;
524 # if (LRCLK_BRG == 1)
525 *IM_BRGC2 = lrclk_brg;
527 # if (LRCLK_BRG == 2)
528 *IM_BRGC3 = lrclk_brg;
530 # if (LRCLK_BRG == 3)
531 *IM_BRGC4 = lrclk_brg;
533 # if (LRCLK_BRG == 4)
534 *IM_BRGC5 = lrclk_brg;
536 # if (LRCLK_BRG == 5)
537 *IM_BRGC6 = lrclk_brg;
539 # if (LRCLK_BRG == 6)
540 *IM_BRGC7 = lrclk_brg;
542 # if (LRCLK_BRG == 7)
543 *IM_BRGC8 = lrclk_brg;
547 * Clear reset on MCLK BRG
550 *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
553 *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
556 *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
559 *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
562 *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
565 *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
568 *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
571 *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
575 * Clear reset on SCLK BRG
578 *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
581 *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
584 *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
587 *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
590 *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
593 *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
596 *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
599 *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
603 * Clear reset on LRCLK BRG
605 # if (LRCLK_BRG == 0)
606 *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
608 # if (LRCLK_BRG == 1)
609 *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
611 # if (LRCLK_BRG == 2)
612 *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
614 # if (LRCLK_BRG == 3)
615 *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
617 # if (LRCLK_BRG == 4)
618 *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
620 # if (LRCLK_BRG == 5)
621 *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
623 # if (LRCLK_BRG == 6)
624 *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
626 # if (LRCLK_BRG == 7)
627 *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
631 * Restore the Interrupt state
640 Daq_BRG_Reset(MCLK_BRG);
641 Daq_BRG_Reset(SCLK_BRG);
642 Daq_BRG_Reset(LRCLK_BRG);
646 void Daq_Start_Clocks(int sample_rate)
649 #ifdef TIGHTEN_UP_BRG_TIMING
650 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
652 register uint mclk_brg; /* MCLK BRG value */
653 register uint sclk_brg; /* SCLK BRG value */
654 register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
655 register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
656 uint lrclk_brg; /* LRCLK BRG value */
657 unsigned long flags; /* Interrupt flags */
658 uint sclk_cnt; /* SCLK count */
659 uint delay_cnt; /* Delay count */
662 # ifdef TIGHTEN_UP_BRG_TIMING
664 * Obtain the enabled MCLK BRG value
667 mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
670 mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
673 mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
676 mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
679 mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
682 mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
685 mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
688 mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
692 * Obtain the enabled SCLK BRG value
695 sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
698 sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
701 sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
704 sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
707 sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
710 sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
713 sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
716 sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
720 * Obtain the enabled LRCLK BRG value
722 # if (LRCLK_BRG == 0)
723 lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
725 # if (LRCLK_BRG == 1)
726 lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
728 # if (LRCLK_BRG == 2)
729 lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
731 # if (LRCLK_BRG == 3)
732 lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
734 # if (LRCLK_BRG == 4)
735 lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
737 # if (LRCLK_BRG == 5)
738 lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
740 # if (LRCLK_BRG == 6)
741 lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
743 # if (LRCLK_BRG == 7)
744 lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
747 /* Save off the real LRCLK value */
748 real_lrclk_brg = lrclk_brg;
750 /* Obtain the current SCLK count */
751 sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
753 /* Compute the delay as a function of SCLK count */
754 delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
755 if (DaqSampleRate == 43402) {
759 /* Clear out the count */
760 temp_lrclk_brg = sclk_brg & ~0x00001FFE;
762 /* Insert the count */
763 temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
766 * Disable interrupt and save the current state
768 flag = disable_interrupts();
774 *IM_BRGC1 = mclk_brg;
777 *IM_BRGC2 = mclk_brg;
780 *IM_BRGC3 = mclk_brg;
783 *IM_BRGC4 = mclk_brg;
786 *IM_BRGC5 = mclk_brg;
789 *IM_BRGC6 = mclk_brg;
792 *IM_BRGC7 = mclk_brg;
795 *IM_BRGC8 = mclk_brg;
802 *IM_BRGC1 = sclk_brg;
805 *IM_BRGC2 = sclk_brg;
808 *IM_BRGC3 = sclk_brg;
811 *IM_BRGC4 = sclk_brg;
814 *IM_BRGC5 = sclk_brg;
817 *IM_BRGC6 = sclk_brg;
820 *IM_BRGC7 = sclk_brg;
823 *IM_BRGC8 = sclk_brg;
827 * Enable LRCLK BRG (1st time - temporary)
829 # if (LRCLK_BRG == 0)
830 *IM_BRGC1 = temp_lrclk_brg;
832 # if (LRCLK_BRG == 1)
833 *IM_BRGC2 = temp_lrclk_brg;
835 # if (LRCLK_BRG == 2)
836 *IM_BRGC3 = temp_lrclk_brg;
838 # if (LRCLK_BRG == 3)
839 *IM_BRGC4 = temp_lrclk_brg;
841 # if (LRCLK_BRG == 4)
842 *IM_BRGC5 = temp_lrclk_brg;
844 # if (LRCLK_BRG == 5)
845 *IM_BRGC6 = temp_lrclk_brg;
847 # if (LRCLK_BRG == 6)
848 *IM_BRGC7 = temp_lrclk_brg;
850 # if (LRCLK_BRG == 7)
851 *IM_BRGC8 = temp_lrclk_brg;
855 * Enable LRCLK BRG (2nd time - permanent)
857 # if (LRCLK_BRG == 0)
858 *IM_BRGC1 = real_lrclk_brg;
860 # if (LRCLK_BRG == 1)
861 *IM_BRGC2 = real_lrclk_brg;
863 # if (LRCLK_BRG == 2)
864 *IM_BRGC3 = real_lrclk_brg;
866 # if (LRCLK_BRG == 3)
867 *IM_BRGC4 = real_lrclk_brg;
869 # if (LRCLK_BRG == 4)
870 *IM_BRGC5 = real_lrclk_brg;
872 # if (LRCLK_BRG == 5)
873 *IM_BRGC6 = real_lrclk_brg;
875 # if (LRCLK_BRG == 6)
876 *IM_BRGC7 = real_lrclk_brg;
878 # if (LRCLK_BRG == 7)
879 *IM_BRGC8 = real_lrclk_brg;
883 * Restore the Interrupt state
892 Daq_BRG_Enable(LRCLK_BRG);
893 Daq_BRG_Enable(SCLK_BRG);
894 Daq_BRG_Enable(MCLK_BRG);
898 void Daq_Display_Clocks(void)
901 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
902 uint mclk_divisor; /* Detected MCLK divisor */
903 uint sclk_divisor; /* Detected SCLK divisor */
906 if (immr->im_brgc4 != 0) {
907 printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
909 (uint)&(immr->im_brgc4),
910 Daq_BRG_Get_Count(3),
911 Daq_BRG_Get_ExtClk(3),
912 Daq_BRG_Get_ExtClk_Description(3));
914 if (immr->im_brgc8 != 0) {
915 printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
917 (uint)&(immr->im_brgc8),
918 Daq_BRG_Get_Count(7),
919 Daq_BRG_Get_ExtClk(7),
920 Daq_BRG_Get_ExtClk_Description(7));
922 if (immr->im_brgc6 != 0) {
923 printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
925 (uint)&(immr->im_brgc6),
926 Daq_BRG_Get_Count(5),
927 Daq_BRG_Get_ExtClk(5),
928 Daq_BRG_Get_ExtClk_Description(5));
930 if (immr->im_brgc1 != 0) {
931 printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
933 (uint)&(immr->im_brgc1),
934 Daq_BRG_Get_Count(0),
935 Daq_BRG_Get_ExtClk(0),
936 Daq_BRG_Get_ExtClk_Description(0));
938 if (immr->im_brgc2 != 0) {
939 printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
941 (uint)&(immr->im_brgc2),
942 Daq_BRG_Get_Count(1),
943 Daq_BRG_Get_ExtClk(1),
944 Daq_BRG_Get_ExtClk_Description(1));
946 if (immr->im_brgc3 != 0) {
947 printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
949 (uint)&(immr->im_brgc3),
950 Daq_BRG_Get_Count(2),
951 Daq_BRG_Get_ExtClk(2),
952 Daq_BRG_Get_ExtClk_Description(2));
954 if (immr->im_brgc5 != 0) {
955 printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
957 (uint)&(immr->im_brgc5),
958 Daq_BRG_Get_Count(4),
959 Daq_BRG_Get_ExtClk(4),
960 Daq_BRG_Get_ExtClk_Description(4));
962 if (immr->im_brgc7 != 0) {
963 printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
965 (uint)&(immr->im_brgc7),
966 Daq_BRG_Get_Count(6),
967 Daq_BRG_Get_ExtClk(6),
968 Daq_BRG_Get_ExtClk_Description(6));
971 # ifdef RUN_SCLK_ON_BRG_INT
972 mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
974 mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
976 # ifdef RUN_LRCLK_ON_BRG_INT
977 sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
979 sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
982 printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
983 printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
984 Daq_BRG_Rate(MCLK_BRG),
986 mclk_divisor * sclk_divisor);
987 # ifdef RUN_SCLK_ON_BRG_INT
988 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
989 Daq_BRG_Rate(SCLK_BRG),
992 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
993 Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
996 # ifdef RUN_LRCLK_ON_BRG_INT
997 printf("\tLRCLK %8d Hz\n",
998 Daq_BRG_Rate(LRCLK_BRG));
1000 # ifdef RUN_SCLK_ON_BRG_INT
1001 printf("\tLRCLK %8d Hz\n",
1002 Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1004 printf("\tLRCLK %8d Hz\n",
1005 Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));