1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
7 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
13 #include <linux/sizes.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/gpio.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
26 #include <asm/mach-types.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* ------------------------------------------------------------------------- */
32 * Miscelaneous platform dependent initialisations
35 #ifdef CONFIG_CMD_NAND
36 static void pm9261_nand_hw_init(void)
39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
43 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
44 writel(csa, &matrix->csa);
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 AT91_SMC_MODE_EXNW_DISABLE |
60 #ifdef CONFIG_SYS_NAND_DBW_16
61 AT91_SMC_MODE_DBW_16 |
62 #else /* CONFIG_SYS_NAND_DBW_8 */
65 AT91_SMC_MODE_TDF_CYCLE(2),
68 at91_periph_clk_enable(ATMEL_ID_PIOA);
69 at91_periph_clk_enable(ATMEL_ID_PIOC);
71 /* Configure RDY/BSY */
72 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
74 /* Enable NandFlash */
75 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
77 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
78 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
83 #ifdef CONFIG_DRIVER_DM9000
84 static void pm9261_dm9000_hw_init(void)
86 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
88 /* Configure SMC CS2 for DM9000 */
89 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
90 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
93 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
94 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
97 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
100 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
101 AT91_SMC_MODE_EXNW_DISABLE |
102 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
103 AT91_SMC_MODE_TDF_CYCLE(1),
106 /* Configure Interrupt pin as input, no pull-up */
107 at91_periph_clk_enable(ATMEL_ID_PIOA);
108 at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
112 int board_early_init_f(void)
119 /* arch number of PM9261-Board */
120 gd->bd->bi_arch_number = MACH_TYPE_PM9261;
122 /* adress of boot parameters */
123 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
125 #ifdef CONFIG_CMD_NAND
126 pm9261_nand_hw_init();
128 #ifdef CONFIG_DRIVER_DM9000
129 pm9261_dm9000_hw_init();
134 #ifdef CONFIG_DRIVER_DM9000
135 int board_eth_init(bd_t *bis)
137 return dm9000_initialize(bis);
143 /* dram_init must store complete ramsize in gd->ram_size */
144 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
149 int dram_init_banksize(void)
151 gd->bd->bi_dram[0].start = PHYS_SDRAM;
152 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
157 #ifdef CONFIG_RESET_PHY_R
160 #ifdef CONFIG_DRIVER_DM9000
162 * Initialize ethernet HW addr prior to starting Linux,
170 #ifdef CONFIG_DISPLAY_BOARDINFO
171 int checkboard (void)
175 printf ("Board : Ronetix PM9261\n");
176 printf ("Crystal frequency: %8s MHz\n",
177 strmhz(buf, get_main_clk_rate()));
178 printf ("CPU clock : %8s MHz\n",
179 strmhz(buf, get_cpu_clk_rate()));
180 printf ("Master clock : %8s MHz\n",
181 strmhz(buf, get_mck_clk_rate()));