2 * board/renesas/ulcb/ulcb.c
3 * This file is ULCB board support.
5 * Copyright (C) 2017 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/rmobile.h>
23 #include <asm/arch/rcar-mstp.h>
24 #include <asm/arch/sh_sdhi.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define CPGWPCR 0xE6150904
31 #define CPGWPR 0xE615090C
33 #define CLK2MHZ(clk) (clk / 1000 / 1000)
36 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
37 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
40 writel(0xA5A5A500, &rwdt->rwtcsra);
41 writel(0xA5A5A500, &swdt->swtcsra);
43 writel(0xA5A50000, CPGWPCR);
44 writel(0xFFFFFFFF, CPGWPR);
47 #define GSX_MSTP112 BIT(12) /* 3DG */
48 #define TMU0_MSTP125 BIT(25) /* secure */
49 #define TMU1_MSTP124 BIT(24) /* non-secure */
50 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
51 #define ETHERAVB_MSTP812 BIT(12)
52 #define DVFS_MSTP926 BIT(26)
53 #define SD0_MSTP314 BIT(14)
54 #define SD1_MSTP313 BIT(13)
55 #define SD2_MSTP312 BIT(12) /* either MMC0 */
57 #define SD0CKCR 0xE6150074
58 #define SD1CKCR 0xE6150078
59 #define SD2CKCR 0xE6150268
60 #define SD3CKCR 0xE615026C
62 int board_early_init_f(void)
64 /* TMU0,1 */ /* which use ? */
65 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
67 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
69 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
71 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
80 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
82 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
88 /* R/- 32 Power status register 2(3DG) */
89 #define SYSC_PWRSR2 0xE6180100
90 /* -/W 32 Power resume control register 2 (3DG) */
91 #define SYSC_PWRONCR2 0xE618010C
95 /* adress of boot parameters */
96 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
98 /* Init PFC controller */
99 #if defined(CONFIG_R8A7795)
100 r8a7795_pinmux_init();
101 #elif defined(CONFIG_R8A7796)
102 r8a7796_pinmux_init();
106 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
109 /* EtherAVB Enable */
111 gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
112 gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
113 gpio_request(GPIO_GFN_AVB_LINK, NULL);
114 gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
115 gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
116 gpio_request(GPIO_GFN_AVB_MDC, NULL);
119 gpio_request(GPIO_IFN_AVB_MDC, NULL);
120 gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
121 gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
122 gpio_request(GPIO_IFN_AVB_LINK, NULL);
123 gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
124 gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
126 gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
128 gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
130 gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
133 gpio_request(GPIO_GP_2_10, NULL);
134 gpio_direction_output(GPIO_GP_2_10, 0);
136 gpio_set_value(GPIO_GP_2_10, 1);
143 static struct eth_pdata salvator_x_ravb_platdata = {
144 .iobase = 0xE6800000,
149 U_BOOT_DEVICE(salvator_x_ravb) = {
151 .platdata = &salvator_x_ravb_platdata,
154 #ifdef CONFIG_SH_SDHI
155 int board_mmc_init(bd_t *bis)
160 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
161 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
162 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
163 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
164 gpio_request(GPIO_GFN_SD0_CLK, NULL);
165 gpio_request(GPIO_GFN_SD0_CMD, NULL);
166 gpio_request(GPIO_GFN_SD0_CD, NULL);
167 gpio_request(GPIO_GFN_SD0_WP, NULL);
169 gpio_request(GPIO_GP_5_2, NULL);
170 gpio_request(GPIO_GP_5_1, NULL);
171 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
172 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
174 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
175 SH_SDHI_QUIRK_64BIT_BUF);
179 /* SDHI1/SDHI2 eMMC */
180 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
181 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
182 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
183 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
184 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
185 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
186 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
187 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
188 gpio_request(GPIO_GFN_SD2_CLK, NULL);
189 #if defined(CONFIG_R8A7795)
190 gpio_request(GPIO_GFN_SD2_CMD, NULL);
191 #elif defined(CONFIG_R8A7796)
192 gpio_request(GPIO_FN_SD2_CMD, NULL);
194 #error Only R8A7795 and R87796 is supported
196 gpio_request(GPIO_GP_5_3, NULL);
197 gpio_request(GPIO_GP_5_9, NULL);
198 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
199 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
201 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
202 SH_SDHI_QUIRK_64BIT_BUF);
210 gd->ram_size = PHYS_SDRAM_1_SIZE;
211 #if (CONFIG_NR_DRAM_BANKS >= 2)
212 gd->ram_size += PHYS_SDRAM_2_SIZE;
214 #if (CONFIG_NR_DRAM_BANKS >= 3)
215 gd->ram_size += PHYS_SDRAM_3_SIZE;
217 #if (CONFIG_NR_DRAM_BANKS >= 4)
218 gd->ram_size += PHYS_SDRAM_4_SIZE;
224 int dram_init_banksize(void)
226 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
227 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
228 #if (CONFIG_NR_DRAM_BANKS >= 2)
229 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
230 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
232 #if (CONFIG_NR_DRAM_BANKS >= 3)
233 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
234 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
236 #if (CONFIG_NR_DRAM_BANKS >= 4)
237 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
238 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
243 const struct rmobile_sysinfo sysinfo = {
244 CONFIG_RCAR_BOARD_STRING
247 static const struct sh_serial_platdata serial_platdata = {
250 .clk = CONFIG_SH_SCIF_CLK_FREQ,
254 U_BOOT_DEVICE(salvator_x_scif2) = {
256 .platdata = &serial_platdata,