1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 #include <asm/processor.h>
9 #include <asm/processor.h>
20 /*------- LBSC -------*/
21 write32 MMSELR_A, MMSELR_D
23 /*------- DBSC2 -------*/
24 write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
25 write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
26 write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
27 write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
28 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
29 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
32 write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
33 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
35 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
36 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
37 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
38 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
39 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
40 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
41 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
42 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
43 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
46 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
47 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
49 write32 DBSC2_DBEN_A, DBSC2_DBEN_D
50 write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
51 write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
52 write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
55 /*------- GPIO -------*/
56 write16 PACR_A, PXCR_D
57 write16 PBCR_A, PXCR_D
58 write16 PCCR_A, PXCR_D
59 write16 PDCR_A, PXCR_D
60 write16 PECR_A, PXCR_D
61 write16 PFCR_A, PXCR_D
62 write16 PGCR_A, PXCR_D
63 write16 PHCR_A, PHCR_D
64 write16 PJCR_A, PJCR_D
65 write16 PKCR_A, PKCR_D
66 write16 PLCR_A, PXCR_D
67 write16 PMCR_A, PMCR_D
68 write16 PNCR_A, PNCR_D
69 write16 PPCR_A, PXCR_D
70 write16 PQCR_A, PXCR_D
71 write16 PRCR_A, PXCR_D
73 write8 PEPUPR_A, PEPUPR_D
74 write8 PHPUPR_A, PHPUPR_D
75 write8 PJPUPR_A, PJPUPR_D
76 write8 PKPUPR_A, PKPUPR_D
77 write8 PLPUPR_A, PLPUPR_D
78 write8 PMPUPR_A, PMPUPR_D
79 write8 PNPUPR_A, PNPUPR_D
80 write16 PPUPR1_A, PPUPR1_D
81 write16 PPUPR2_A, PPUPR2_D
82 write16 P1MSELR_A, P1MSELR_D
83 write16 P2MSELR_A, P2MSELR_D
85 /*------- LBSC -------*/
87 write32 CS0BCR_A, CS0BCR_D
88 write32 CS0WCR_A, CS0WCR_D
89 write32 CS1BCR_A, CS1BCR_D
90 write32 CS1WCR_A, CS1WCR_D
91 write32 CS4BCR_A, CS4BCR_D
92 write32 CS4WCR_A, CS4WCR_D
96 mov.l PASCR_32BIT_MODE, r1
100 write32 CS2BCR_A, CS_USB_BCR_D
101 write32 CS2WCR_A, CS_USB_WCR_D
102 write32 CS3BCR_A, CS_SD_BCR_D
103 write32 CS3WCR_A, CS_SD_WCR_D
104 write32 CS5BCR_A, CS_I2C_BCR_D
105 write32 CS5WCR_A, CS_I2C_WCR_D
106 write32 CS6BCR_A, CS0BCR_D
107 write32 CS6WCR_A, CS0WCR_D
112 write32 CS5BCR_A, CS_USB_BCR_D
113 write32 CS5WCR_A, CS_USB_WCR_D
114 write32 CS6BCR_A, CS_SD_BCR_D
115 write32 CS6WCR_A, CS_SD_WCR_D
118 #if defined(CONFIG_SH_32BIT)
119 /*------- set PMB -------*/
120 write32 PASCR_A, PASCR_29BIT_D
121 write32 MMUCR_A, MMUCR_D
123 /*****************************************************************
124 * ent virt phys v sz c wt
125 * 0 0xa0000000 0x00000000 1 64M 0 0
126 * 1 0xa4000000 0x04000000 1 16M 0 0
127 * 2 0xa6000000 0x08000000 1 16M 0 0
128 * 9 0x88000000 0x48000000 1 128M 1 1
129 * 10 0x90000000 0x50000000 1 128M 1 1
130 * 11 0x98000000 0x58000000 1 128M 1 1
131 * 13 0xa8000000 0x48000000 1 128M 0 0
132 * 14 0xb0000000 0x50000000 1 128M 0 0
133 * 15 0xb8000000 0x58000000 1 128M 0 0
135 write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
136 write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
137 write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
138 write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
139 write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
140 write32 PMB_DATA_USB_A, PMB_DATA_USB_D
141 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
142 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
143 write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
144 write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
145 write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
146 write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
147 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
148 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
149 write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
150 write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
151 write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
152 write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
154 write32 PASCR_A, PASCR_INIT
166 /*------- GPIO -------*/
167 /* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
183 PPUPR1_D: .word 0xffbf
184 PPUPR2_D: .word 0xff00
185 P1MSELR_D: .word 0x3780
186 P2MSELR_D: .word 0x0000
188 #define GPIO_BASE 0xffe70000
189 PACR_A: .long GPIO_BASE + 0x00
190 PBCR_A: .long GPIO_BASE + 0x02
191 PCCR_A: .long GPIO_BASE + 0x04
192 PDCR_A: .long GPIO_BASE + 0x06
193 PECR_A: .long GPIO_BASE + 0x08
194 PFCR_A: .long GPIO_BASE + 0x0a
195 PGCR_A: .long GPIO_BASE + 0x0c
196 PHCR_A: .long GPIO_BASE + 0x0e
197 PJCR_A: .long GPIO_BASE + 0x10
198 PKCR_A: .long GPIO_BASE + 0x12
199 PLCR_A: .long GPIO_BASE + 0x14
200 PMCR_A: .long GPIO_BASE + 0x16
201 PNCR_A: .long GPIO_BASE + 0x18
202 PPCR_A: .long GPIO_BASE + 0x1a
203 PQCR_A: .long GPIO_BASE + 0x1c
204 PRCR_A: .long GPIO_BASE + 0x1e
205 PEPUPR_A: .long GPIO_BASE + 0x48
206 PHPUPR_A: .long GPIO_BASE + 0x4e
207 PJPUPR_A: .long GPIO_BASE + 0x50
208 PKPUPR_A: .long GPIO_BASE + 0x52
209 PLPUPR_A: .long GPIO_BASE + 0x54
210 PMPUPR_A: .long GPIO_BASE + 0x56
211 PNPUPR_A: .long GPIO_BASE + 0x58
212 PPUPR1_A: .long GPIO_BASE + 0x60
213 PPUPR2_A: .long GPIO_BASE + 0x62
214 P1MSELR_A: .long GPIO_BASE + 0x80
215 P2MSELR_A: .long GPIO_BASE + 0x82
217 MMSELR_A: .long 0xfc400020
218 #if defined(CONFIG_SH_32BIT)
219 MMSELR_D: .long 0xa5a50005
221 MMSELR_D: .long 0xa5a50002
224 /*------- DBSC2 -------*/
225 #define DBSC2_BASE 0xfe800000
226 DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
227 DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
228 DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
229 DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
230 DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
231 DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
232 DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
233 DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
234 DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
235 DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
236 DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
237 DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
238 DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
239 DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
240 DDR_DUMMY_ACCESS_A: .long 0x40000000
242 DBSC2_DBCONF_D: .long 0x00630002
243 DBSC2_DBTR0_D: .long 0x050b1f04
244 DBSC2_DBTR1_D: .long 0x00040204
245 DBSC2_DBTR2_D: .long 0x02100308
246 DBSC2_DBFREQ_D1: .long 0x00000000
247 DBSC2_DBFREQ_D2: .long 0x00000100
248 DBSC2_DBDICODTOCD_D:.long 0x000f0907
250 DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
251 DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
252 DBSC2_DBCMDCNT_D_REF: .long 0x00000004
254 DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
255 DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
256 DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
257 DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
258 DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
259 DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
261 DBSC2_DBEN_D: .long 0x00000001
263 DBSC2_DBPDCNT0_D3: .long 0x00000080
264 DBSC2_DBRFCNT1_D: .long 0x00000926
265 DBSC2_DBRFCNT2_D: .long 0x00fe00fe
266 DBSC2_DBRFCNT0_D: .long 0x00010000
268 WAIT_200US: .long 33333
270 /*------- LBSC -------*/
271 PASCR_A: .long 0xff000070
272 PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
275 CS0BCR_A: .long CS0BCR
276 CS0WCR_A: .long CS0WCR
277 CS1BCR_A: .long CS1BCR
278 CS1WCR_A: .long CS1WCR
279 CS2BCR_A: .long CS2BCR
280 CS2WCR_A: .long CS2WCR
281 CS3BCR_A: .long CS3BCR
282 CS3WCR_A: .long CS3WCR
283 CS4BCR_A: .long CS4BCR
284 CS4WCR_A: .long CS4WCR
285 CS5BCR_A: .long CS5BCR
286 CS5WCR_A: .long CS5WCR
287 CS6BCR_A: .long CS6BCR
288 CS6WCR_A: .long CS6WCR
290 BCR_D: .long 0x80000003
291 CS0BCR_D: .long 0x22222340
292 CS0WCR_D: .long 0x00111118
293 CS1BCR_D: .long 0x11111100
294 CS1WCR_D: .long 0x33333303
295 CS4BCR_D: .long 0x11111300
296 CS4WCR_D: .long 0x00101012
298 /* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
299 CS_USB_BCR_D: .long 0x11111200
300 CS_USB_WCR_D: .long 0x00020005
302 /* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
303 CS_SD_BCR_D: .long 0x00000300
304 CS_SD_WCR_D: .long 0x00030108
306 /* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
307 CS_I2C_BCR_D: .long 0x11111100
308 CS_I2C_WCR_D: .long 0x00000003
310 #if defined(CONFIG_SH_32BIT)
311 /*------- set PMB -------*/
312 PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
313 PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
314 PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
315 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
316 PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
317 PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
318 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
319 PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
320 PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
322 PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
323 PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
324 PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
325 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
326 PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
327 PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
328 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
329 PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
330 PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
332 PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
333 PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
334 PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
335 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
336 PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
337 PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
338 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
339 PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
340 PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
342 /* ppn ub v s1 s0 c wt */
343 PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
344 PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
345 PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
346 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
347 PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
348 PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
349 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
350 PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
351 PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
353 DUMMY_ADDR: .long 0xa0000000
354 PASCR_29BIT_D: .long 0x00000000
355 PASCR_INIT: .long 0x80000080 /* check booting mode */
356 MMUCR_A: .long 0xff000010
357 MMUCR_D: .long 0x00000004 /* clear ITLB */
358 #endif /* CONFIG_SH_32BIT */
360 CCR_A: .long 0xff00001c
361 CCR_D: .long 0x0000090b